PRELIMINARY
PFM18030
SPECIFICATION
18051880 MHz, 30W, 2Stage Power Module
EnhancementMode Lateral MOSFETs
This versatile DCS module provides excellent linearity and efficiency in a
lowcost surface mount package. The PFM18030SM includes two stages
Package Type: Surface Mount
of amplification, along with internal sense FETs that are on the same
silicon die as the RF devices. These thermally coupled sense FETs
PN: PFM18030SM
simplify the task of bias temperature compensation of the overall amplifier.
The module includes RF input, interstage, and output matching elements.
The source and load impedances required for optimum operation of the
module are much higher (and simpler to realize) than for unmatched Si
LDMOS transistors of similar performance.
The surface mount package base is typically soldered to a conventional
PCB pad with an array of via holes for grounding and thermal sinking of
the module. Optimized internal construction supports low FET channel
temperature for reliable operation.
Package Type: Flange
PN: PFM18030F
·
29 dB Gain
·
30 Watts Peak Output Power
·
Internal Tracking FETs
(for improved bias control)
·
IS95 CDMA Performance
5 Watts Average Output Level
20% Power Added Efficiency
–49 dBc ACPR
Module Schematic Diagram
Module Substrate
Q1 Die Carrier
Q1
Q2 Die Carrier
Q2
Drain 2
RF OUT
Output
Match
Lead
Gate 1
RF IN
Lead
Input
Match
Output
Match
Input
Match
S1
S2
Sense S1
Lead
Gate 2
Lead
Sense S2
Lead
D1
Lead
Note: Additionally, there are 250 KOhm resistors connected in shunt with all leads, to enhance ESD protection.
Page 1 of 13
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 3
PFM18030
Electrical Specification
Parameter
Min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Operating Frequency
Gain
Gain Compression at
Pout =30 Watts
Gain Flatness over any
30 MHz bandwidth
Deviation from Linear
Phase over any 30
MHz bandwidth
Group Delay
ACPR with IS95A
CDMA Pave = 5 W
Efficiency under IS95
Protocol, Pave = 5 W
DC Drain Supply
Voltage
Operating
Temperature Range
(base temperature)
Gain Variation versus
Temperature
Output Mismatch
Stress
Stability
Theta jc (channel)
Quiescent Currents
a) Q1
b) Q2
Sense FET Periphery
Ratio
a) Stg 1 Track
b) Stg 2 Track
ESD Protection
a) Human Body Model
b) Machine Model
1805
27.5
45
18
24
40
60
Limits
Typ
29.5
0.8
± 0.1
± 0.8
3.1
49
20
27
0.033
1.9
73
235
Units
Max
1880
32
1.5
± 0.3
± 1.2
3.7
30
+115
30
2.1
MHz
dB
dB
dB
°
nanosec
dBc
%
Volts
°C
dB/°C
Watts
CW
dBc
°C/W
mA
mA
Note 1.
Comments
Pulsed CW compression measurement
(12
msec pulse, 120 msec period, 10%
duty cycle).
Note 1.
Note 1
Includes delay of test fixture
(~0.6 nanosec.). Note 1
Note 4. Refer to applications data for
performance with other protocols.
Note 4.
Testing for conformance with RF
specifications is at +27 V.
Testing for conformance with RF
specification is at +25
°C.
Bias quiescent currents held constant.
VSWR 10:1, all phase angles. No
degradation in output power before &
after test.
0<Pout<44.8 dBm CW, 3:1 VSWR
Theta jc is for output device. Verified
with IR scan. Note 3.
These DC quiescent currents are typical
of the levels that produce optimum
linearity for CDMA protocol.
Ratio of sense FET current, relative to RF
FET current. Ratios are: Stg 1: 33:1;
Stg 2: 58:1 Gates of sense & RF FETs
are DC connected. Measured with no RF
signal present.
a) 2000V, 100 pF, 1500 Ohms
b) 400V, 200 pF, zero Ohms
Mil STD 883E, Method 3015 for Human
Body Model and for Machine Model.
16
3.0
1.7
%
%
17
Class 1
Class M3
Page 2 of 13
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 3
PFM18030
Electrical Specification (Continued)
MAXIMUM RATINGS
Rating
19
DC Drain Supply
a) DraintoSource Voltage, (V
GS
=0), D1 & D2
& Track D1 & Track D2
b) Normal Operation (Class AB operation)
DC Gate Supply
a) Gatetosource Voltage (V
DS
=0)
Normal Operation (Class AB operation)
RF Input Power
Maximum Power Dissipation (T
£
+85
°C)
a) Derate above +85
°C base temperature.
Maximum Channel Operating Temperature
Storage Temperature Range
Symbol
V
DS
V
D_SUPPLY
V
GS
V
G_SUPPLY
P
IN
P
TOTAL
T
CH
T
STG
Value
+50
+30
0.5<V
GS
<+15
0<V
GS
<+6
+25
65
0.7
+200
40 to +150
Units
Volts DC
Volts DC
Volts DC
Volts DC
dBm
Watts
Watts/°C
°C
°C
20
21
22
23
24
RECOMMENDED SOURCE AND LOAD IMPEDANCES
Impedance
Nominal Source
Impedance for
Optimum Operation
Nominal Load
Impedance for
Optimum Operation
19 – 5
Units
Ohms
Comments
Matched for nearoptimum linearity and gain flatness.
Impedance is looking from the module input lead into the
input matching circuit. Reference plane is 0.105 inches from
the input end (case edge)of the module.
Matched for nearoptimum linearity under CDMA protocol.
Impedance is from the module output lead looking into the
output matching circuit. Reference plane is 0.105 inches from
the output end (case edge) of the module.
22 + j6
Ohms
Specification Notes:
1) Power testing of gain, gain flatness phase and time delay measurements will be at small signal. Production testing
will be for smallsignal conditions (nominal 0 dBm input level) with the frequency swept through the indicated band.
2) The module is mounted in a test fixture with external matching elements for all testing. Quiescent current bias
conditions are those appropriate for minimum ACPR under CDMA protocol. Supply voltage for all tests is
+27 volts DC. Testing is at +25
°C unless otherwise specified.
3) Theta jc is measured with a package mounting (base) temp of +85
°C, and with 10 Watts CW output.
4) Pout=5Watts average; IS95A protocol: IS95 Forward Link PPS+ 9CH.
ACPR conditions: a) 900 kHz offset, 30 kHz BW, b) 2.75 MHz offset, 1 MHz BW.
5) Sense FETs are scaled versions of the main RF FETs, formed from electrically isolated cells at end of the RF
structure. Current scales according to periphery (threshold voltages offset is less than
±150 millivolts between
adjacent devices). RF & Sense FET gates and sources are DC connected. Drains are DC isolated. Leads S1 & S2
are DC connected to drains of sense FETs 1 & 2. Sources are connected to package base. Sense FETs are
electrically isolated from the RF signals.
Page 3 of 13
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 3
PFM18030
Typical Module Performance
T=+25
°C, unless otherwise noted. Data is for module in a test fixture with external matching elements. See following
page for test fixture details.
Typical Small Signal Gain vs. Frequency
31
10
IM3L
Typical CW 2Tone Intermods vs. Output Power
(F1=1840, F2=1841 MHz)
Intermodulation Distortion (dBc)
30
20
IM3U
IM5L
29
30
IM5U
IM7L
IM7U
28
40
27
50
26
1730 1755 1
780 1805 1830 1
855 1880 1905 1930 1955 1980 2005
60
F requency (M Hz)
70
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Average Output Power (dBm)
Input & Output Return Loss vs. Frequency
Typical CW 2Tone Intermods vs. Output Power
1
1
(F1=1805, F2=1806 MHz)
10
Intermodulation Distortion (dBc)
IM3L
Return Loss (dB)
3
OUTPUT
5
7
9
INPUT
11
13
15
1780
20
30
40
50
60
70
30
IM3U
IM5L
IM5U
IM7L
IM7U
1805
1830
1855
1880
1905
1930
1955
Frequency (MHz)
31
32
33
34
35
36
37
38
39
40
41
42
43
Average Output Power (dBm)
Typical CW Gain vs Swept CW Output Power,
with Various Bias Conditions (F=1840 MHz)
31
Typical CW 2Tone Intermods vs. Output Power
(
F1=1880, F2=1881 MHz)
10
IM3L
Intermodulation Distortion (dBc)
30
Best for 2Tone IMDs
29
20
30
40
50
60
70
30
IM3U
IM5L
IM5U
IM7L
IM7U
Gain (dB)
28
27
26
25
G(52/184)
24
27
29
31
33
35
37
39
41
43
45
G(65/230)
G(58/207)
G(71/253)
31
32
33
34
35
36
37
38
39
40
41
42
43
CW Swept Output Power (dBm)
Average Output Power (dBm)
Page 4 of 13
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 3
PFM18030
PFM18030SM Package Outline
PFM18030F Package Outline
Page 5 of 13
Specifications subject to change without notice. U.S. Patent No. 6,822,321
http://www.cree.com/
Rev. 3
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