PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
Rev. 01 — 25 June 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP71NQ03LT in SOT78 (TO-220AB)
PHB71NQ03LT in SOT404 (D
2
-PAK)
PHD71NQ03LT in SOT428 (D-PAK).
1.2 Features
s
Logic level compatible
s
Low gate charge
1.3 Applications
s
DC to DC converters
s
Switched mode power supplies
1.4 Quick reference data
s
V
DS
= 30 V
s
P
tot
= 120 W
s
I
D
= 75 A
s
R
DSon
≤
10 mΩ
2. Pinning information
Table 1:
1
2
3
mb
Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Simplified outline
[1]
mb
mb
mb
Pin Description
gate (g)
drain (d)
source (s)
mounting base,
connected to drain (d)
Symbol
d
g
s
2
2
1
MBK106
MBB076
1
3
MBK116
3
MBK091
Top view
1 2 3
SOT78 (TO-220)
[1]
SOT404 (D
2
-PAK)
SOT428 (D-PAK)
It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
peak gate-source voltage
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
mb
= 25
°C
peak source (diode forward) current T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
t
p
≤
50
µs;
pulsed; duty cycle = 25 %
T
mb
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 10 V;
Figure 2
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
175
°C
25
°C ≤
T
j
≤
175
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
-
−55
−55
-
-
Max
30
30
±20
±25
75
57.7
240
120
+175
+175
75
57.7
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 09821
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 25 June 2002
2 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
120
Pder
(%)
80
03aa16
120
Ider
(%)
80
03ai74
40
40
0
0
50
100
150
200
Tmb (°C)
0
0
50
100
150
200
Tmb (°C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
103
ID
(A)
03ai76
Limit RDSon = VDS / ID
tp = 10
µs
102
100
µs
DC
10
1 ms
10 ms
1
1
10
VDS (V)
102
T
mb
= 25
°C;
I
DM
is single pulse; V
GS
= 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 09821
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 25 June 2002
3 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
4. Thermal characteristics
Table 3:
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
Min Typ Max Unit
-
-
-
-
-
60
75
50
1.25 K/W
-
-
-
K/W
K/W
K/W
thermal resistance from junction to mounting base
Figure 4
thermal resistance from junction to ambient
SOT78
SOT428
SOT404 and SOT428
vertical in still air
SOT428 minimum footprint;
mounted on a PCB
SOT404 minimum footprint;
mounted on a PCB
Symbol Parameter
4.1 Transient thermal impedance
10
Zth(j-mb)
(K/W)
03ai75
1
δ
= 0.5
0.2
0.1
10-1
0.05
0.02
single pulse
10-2
10-5
tp
T
10-4
10-3
10-2
tp (s)
10-1
t
P
δ
=
tp
T
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 09821
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 25 June 2002
4 of 14
Philips Semiconductors
PHP/PHB/PHD71NQ03LT
TrenchMOS™ logic level FET
5. Characteristics
Table 4:
Characteristics
T
j
= 25
°
C unless otherwise specified
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 175
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 175
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 25 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 175
°C
V
GS
= 10 V; I
D
= 25 A;
Figure 7
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 25 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 10 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V
V
DD
= 15 V; I
D
= 25 A; V
GS
= 4.5 V; R
G
= 5.6
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
I
D
= 50 A; V
DD
= 15 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
13.2
5.3
4.6
330
140
15
150
13.5
18
0.9
29
20
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
-
12
21.6
8
15.2
27.4
10
mΩ
mΩ
mΩ
-
-
-
0.05
-
10
1
500
100
µA
µA
nA
1
0.6
-
1.9
-
-
2.5
-
2.9
V
V
V
30
27
-
-
-
-
V
V
Conditions
Min
Typ
Max
Unit
1220 -
Source-drain diode
9397 750 09821
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 25 June 2002
5 of 14
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