Isolated DC/DC controller IC
Built-in Secondary-side Driver
with Synchronous Rectification
Active Clamp PWM Controller
BD8325FVT-M
●General
Description
BD8325FVT-M is a PWM controller intended for Active
clamp, current-mode isolated switching regulator.
This controller provides control outputs for driving
primary-side MOSFET, and outputs with adjustable delay,
which can be used for driving synchronous rectifier
MOSFET on the secondary-side.
Its maximum input voltage is 20V. External startup
regulator can be set at high voltage.
●Applications
■
High efficiency/ large current isolated DC/DC
(VINmax=100V)
■
Cellular base station
■
Industrial power supplies
■
Car application
■
10W to 700W SMPS
●Package
TSSOP-B30
W(Typ) x D(Typ) x H(Max)
10.00mm x 7.60mm x 1.00mm
●Features
■
Ideal for Active Clamp /Rest Forward/Flyback
converter
■
Current-mode Control with Dual Mode Over-Current
Protection
■
Synchronization to External Clock
■
Programmable Dead-Time (Turn-On/Turn-Off)
between MAIN and AUX MOSFET by External
Resistor
■
Have Control Outputs for Driving Primary Side
MOSFET; Have Outputs with Adjustable Time for
Driving Synchronous Rectifier MOSFET in
Secondary Side (OUT2F, OUT2R pin)
■
Programmable Oscillator Frequency and Maximum
Duty Cycle by External Resistor
■
Programmable Soft-Start Time by External
Capacitor
■
Programmable Slope Compensation by External
Resistor
■
A Variety of Protection
First Over-Current Protection (Pulse-by-Pulse mode)
Second Over-Current Protection (HICCUP mode)
VCC_UVLO (Input Under-Voltage Protection)
LINE_UVLO (Line Under-Voltage Protection)
●Typical
Application Circuits
VLINE
Wake
up
REG
VOUT
REG
VCC/VDD
CS
LINEUV
VREF
SS
FB
SAWH
OUT
RTON
RTOFF
RDELON
RDELOFF OUT2F
RDELSLF
RDELSLR1
RDELSLR2 OUT2R
CLKOUT
SYNC
GND
AUX
PGND
ERROR
AMP
Fig.1 Typical Application Circuit
○
Structure：Silicon Monolithic Integrated Circuit
○
This product has no designed protection against radioactive rays.
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BD8325FVT
●
Pin Configuration
(TOP VIEW)
GND
CS2
CS1
LINEUV
FB
VREF
SS/SD
RSLP
RDELON
RDELOFF2
RTON
RTOFF
RDELSLF
RDELOFF1
RDELSLR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLKOUT
SAWH
SYNC
VCC
VDD
N.C.
AUX
N.C.
OUT
N.C.
OUT2F
N.C.
OUT2R
N.C.
PGND
Fig.2 Pin Configuration (TOP VIEW)
●Pin
Description
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol
GND
CS2
CS1
LINEUV
FB
VREF
SS/SD
RSLP
RDELON
RDELOFF2
RTON
RTOFF
RDELSLF
RDELOFF1
RDELSLR
Description
GND pin
HICCUP mode OCP detecting pin
Current feedback & pulse-by-pulse
OCP detecting pin
UVLO detecting pin
Feedback voltage input pin
5V regulator output pin
Soft-Start time set pin
Slope compensation ramp set pin
OUT rise/fall timing set pin
AUX fall timing set pin
Switching frequency and
ON time set pin
Switching frequency and
OFF time set pin
OUT2F rise/fall timing set pin
AUX rise timing set pin
OUT2R rise timing set pin
No
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
PGND
N.C
OUT2R
N.C
OUT2F
N.C
OUT
N.C
AUX
N.C
VDD
VCC
SYNC
SAWH
CLKOUT
Description
PWR GND
N.C
Gate control pin for driving
freewheel NMOS in secondary side
N.C
Gate control pin for driving forward
NMOS in secondary side
N.C
Gate control pin for driving MAIN
PWM NMOS in primary side
N.C
Gate control pin for driving
active-clamp PMOS in primary side
N.C
Power pin of FET driver
Power pin of IC controller block
Synchronization signal input pin
Triangular wave amplitude set pin
CLK output pin
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BD8325FVT
●Block
Diagram
SYNC CLKOUT
④
SAWH
VREF
RSLP
RDELON
RDELOFF1
RDELOFF2
RDELSLF
RDELSLR
SAW
⑤
①
VREF
INTERNAL_REG
Current Sourse
IREF
5uA
LINEUVLO
③
LINEUV
1.2V
VCCUVLO
CLOCK
START
END
VREFUVLO
VCC
VDD
⑥
⑬
RTON
RTOFF
VREF
Duty0
⑮
⑭
SLP
OUT
PGND
②
PWM
Signal
⑫
5×I
SLP
S Q
R QB
TURN
ON/OFF
DELAY
AUX
OUT2F
PGND
CS1
0.48V
CLKOUT
0.46V
OCP1
PWM offset
0.5V
PGND
PGND
VREF
OUT2R
⑨
⑩
XRESET
SS/SD
15uA
⑪
15uA
PGND
CS2
OCP2
CLKOUT
1.2V
⑧
R
4×R
OCP2
VCC_UVLO
VREF_UVLO
GND
⑦
LINEUV
TSD
SOFT START
&
SOFT STOP
FB SS/SD
Fig.3 Block Diagram
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BD8325FVT
●Description
of Blocks
①Internal
Power Supply
This is a regulator for powering the internal circuits via VCC. There is no direct output pin from this block.
②LDO
Block
This is the 5V regulator that can provide the power supply for startup block. It should be bypassed by 0.1uF~0.47uF for
stability. The circuit is utilized for the pull-up power supply of FB pin and the power supply for SAWOSC, CLK and SS/SD
block. UVLO function is built-in (4.5V Typ). Once UVLO signal is detected, OUT, AUX, OUT2F and OUT2R pins turn L,
and the capacitor connected to SS/SD pin is also discharged instantaneously. The short current between VREF and
GND is 12mA (Typ).
③UVLO
block
This is UVLO detection circuit of VCC, LINE and LDO.
The IC starts up and shuts down based on the sequence on timing chart.
When LINE UVLO signal is reset, 5uA current flows through LINEUV pin while when LINE UVLO is detected, the current
is 0uA. It is possible to adjust the HYS value through the external resistor. Moreover, VCC and VREF’s UVLO
comparators have built-in minimum of 2us noise filters for avoiding error detection.
④Timing
Set Block
For simplicity of application, the adjustable function can be achieved through external resistor:
・switching
timing of OUT, AUX, OUT2F and OUT2R pin
→ resistors connected from RDELON, RDELOFF1, RDELOFF2, RDELSLF, RDELSLR pin (1.6V typ) to ground
・oscillator
frequency and MAX Duty
→ resistors connected from RTON and RTOFF pin (1.6V typ) to ground
・slope
compensation amplitude
→ resistor connected from RSLP pin (maximum value of sawtooth wave: 2.5V (typ)) to ground
There is a built-in open detection function such that when it is activated, the outputs are terminated. This is to avoid the
pin opening caused by the incorrect mounting of external resistor.
⑤Synchronization
CLK transmitter
When multiple ICs will be use, the synchronization function is implemented so that the frequency remains synchronous.
The master IC provides CLKOUT signal to the slave IC through SYNC pin, and in turn, the slave IC and master IC’s
frequency can be synchronized. The transmitter includes the I/O part of CLK and SYNC pin. By means of extracting the
frequency (at the rising edge) only, the MaxDuty can be set. There is H-side and L-side resistors connected to CLKOUT
pin with a value of 0.6kΩ.
⑥SAWOSC
block
The circuit is used for generating clock, duty and slope signal. In the stand-alone operation (external synchronization
inactivated) the voltage of SAWH pin, which determines the amplitude of internal triangular wave, is 2.65V (typ). During
the external synchronization operation, the internal circuits control the SAWH voltage to synchronize with the external
clock. LVP circuit is applied to SAWH pin, and the detection and reset voltage are 1.35V (typ) and 2.6V (typ). As soon as
SAWH LVP signal is detected, OUT, AUX, OUT2F and OUT2R turn L and SS/SD is discharged instantaneously, and
SAWH is pre-charged (10kΩ).
⑦Feedback
block
The voltage of SS/SD from block
⑪
is compared with FB voltage; the lower voltage enters the PWM signal generator.
⑧CS1,
CS2 control block
This is the block intended for OCP detection.
When CS1 exceeds 0.48V, OCP1 signal is produced and RESET flag of Latch circuit (⑫) is activated. In addition,
OUT=L, AUX=L, OUT2F=L, OUT2R=H and the power transfer from input to output is terminated momentarily. When the
CLK enters into next cycle, the power transfer starts again. As the new cycle starts, the low-side NMOS switch connected
to CS1 pin is ON when CLKOUT=H in order to make sure that the reset signal is removed. With the series of action,
pulse-by-pulse mode OCP protection is observed as shown in the example application design.
When CS2 voltage exceeds 1.2V (typ), OCP2 signal is detected, the IC enters into SOFT_STOP mode and SS/SD pin
starts to be discharged with 15uA current. As CS2 voltage drops to 1.2V (typ) and SS/SD≦ 0.5V, the IC returns to
SOFT_START mode and starts up. Like CS1, the low side NMOS switch connected to CS2 is ON when CLKOUT=H. As
shown in the example application design, if the output is shorted to ground, then the SOFT_START mode and
SOFT_STOP mode alternate, the chip’s HICCUP OCP protection operates.
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BD8325FVT
⑨PWM
signal generator
Through the comparator, CS1 related signal is compared with the lower voltage of SS/SD（⑦）and FB pin, and RESET
signal for Latch circuit (⑫) is produced. To be precise, the CS1 level +0.5V and the lower of SS/SD and FB level’s 1/5
are compared and the output pulse is entered into Latch circuit. In addition, when FB is lowered and SS/SD drops to
2.3V (typ), Duty0 signal turns H and RESET signal continues outputting, switching is terminated and Duty is turned to 0%.
Once the switching restarts, Duty0 will not turn H unless the voltage drops to the hysteresis voltage, 2.225V (typ).
⑩RESET
condition generator
According to the outputs from each protection circuit, the block controls the signal as shown below:
(1) SS/SD 15uA charge, 15uA discharge, instantaneous discharge
(2) PWM signal（OUT, AUX, OUT2F, OUT2R）OFF
⑪SS
charge/discharge controller
According to whether the protection operation is detected, the operation is shown as (1)
½
(3)
(1) 15uA Charge (SOFT_START) condition: when VCC UVLO, VREF UVLO, LINE UVLO, TSD, CS2, SAWH LVP
and external R-OPEN protections are not detected. SS/SD is clamped to VREF5V level.
(2) 15uA Discharge (SOFT_STOP) condition: when LINE, TSD and CS2 protections are detected.
Once detected, the signal is latched. The IC will not restore to SOFT START mode unless SS/SD is 0.5V.
(3) Instantaneous Discharge (discharge resistor R=0.5kΩ) condition: when VCC UVLO, VREF UVLO, SAWH LVP
and R-OPEN protection are detected.
⑫PWM
signal latch block
The reference pulse signal of each output pulse is generated by SR-Flipflop.
SET: internal clock signal
RESET: PWM output signal or OCP1 signal or CLKOUT signal (Max Duty)
⑬Turn-on
delay/Turn-off delay time generator
According to the dead-times, which are set by the external resistor on OUT, AUX, OUT2F and OUT2R pin in block
④,
dead-times are applied to PWM signal (⑫).
⑭PREDRIVER
The level of VREF5V is shifted to VDD level.
⑮POWMOS
This is the driver’s output stage for driving external MOSFET. It is constituted by NMOS and PMOS and the power supply
is VDD (absolute maximum rating is 20V).
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