Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
FEATURES
•
85 ps part-to-part skew typical
•
20 ps output-to-output skew typical
•
Differential design
•
V
BB
output
•
Voltage and temperature compensated outputs
•
Low voltage V
EE
range of –2.25 V to –3.8 V
•
75 kΩ input pull-down resistors
•
Form, fit, and function compatible with MC100EP210
DESCRIPTION
The PCK210 is a low skew 1-to-5 dual differential driver, designed
with clock distribution in mind. The input signals can be either
differential or single-ended if the V
BB
output is used. The signal is
fanned out to 5 identical differential outputs.
The PCK210 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to
minimize gate-to-gate skew within a device, and empirical modeling
is used to determine process control limits that ensure consistent
t
PD
distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met, it is necessary that
both sides of the differential output are terminated into 50
Ω,
even if
only one side is being used. In most applications, all ten differential
pairs will be used, and therefore terminated. In the case where fewer
than ten pairs are used, it is necessary to terminate at least the
output pairs on the same package side as the pair(s) being used on
that side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order of
10–20 ps) of the output(s) being used, which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The PCK210, as with most other ECL devices, can be operated
from a positive V
CC
supply in PECL mode. This allows the PCK210
to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Designers can take advantage of the PCK210’s
performance to distribute low skew clocks across the backplane or
the board. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies.
The PCK210 may be driven single-endedly utilizing the V
BB
bias
output with the CLKA or CLKB input. If a single-ended signal is to be
used, the V
BB
pin should be connected to the CLKA or CLKB input
and bypassed to ground via a 0.01
µF
capacitor. The V
BB
output
can only source/sink 0.3 mA, therefore, it should be used as a
switching reference for the PCK210 only. Part-to-part skew
specifications are not guaranteed when driving the PCK210
single-endedly.
PINNING
Pin configurations
V
CCO
QA0
QA0
QA1
QA1
QA2
QA2
26
V
CCO
25
32
31
30
29
28
V
CC
n.c.
CLKA
CLKA
V
BB
CLKB
CLKB
V
EE
1
2
3
4
27
24 QA3
23 QA3
22 QA4
21 QA4
PCK210BD
5
6
7
8
20 QB0
19 QB0
18 QB1
17 QB1
QB4 10
QB3 12
QB3 13
QB2 14
QB2 15
V
CCO
16
V
CCO
QB4
11
9
SW00909
Figure 1. LQFP32 pin configuration
V
CCO
32
31
30
29
28
27
26
25
V
CCO
QA0
QA0
QA1
QA1
QA2
QA2
V
CC
n.c.
CLKA
CLKA
V
BB
CLKB
CLKB
V
EE
1
2
3
4
5
6
7
8
10
12
13
14
15
16
11
9
24
23
22
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
PCK210BS
(TOP VIEW)
21
20
19
18
17
V
CCO
Figure 2. HVQFN32 pin configuration
ORDERING INFORMATION
Type number
n mber
PCK210BD
PCK210BS
Package
Name
LQFP32
HVQFN32
Description
plastic low profile quad flat package; 32 leads; body 7
×
7
×
1.4 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5
×
5
×
0.85 mm
Version
SOT358-1
SOT617-1
Temperature
p
range
–40
°C
to +85
°C
–40
°C
to +85
°C
2004 Apr 23
2
V
CCO
QB4
QB4
QB3
QB3
QB2
QB2
SW02237
Philips Semiconductors
Product data
Low voltage dual 1:5 differential
ECL/PECL clock driver
PCK210
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
CC
V
I
I
IN
T
stg
ESD
HBM
ESD
MM
ESD
CDM
Supply voltage
Input voltage
Input current
Storage temperature range
Electrostatic discharge (Human Body Model; 1.5 kΩ, 100 pF)
Electrostatic discharge (Machine Model; 0 kΩ, 100 pF)
Electrostatic discharge (Charge Device Model)
PARAMETER
LIMITS
MIN
–0.3
–0.3
–
–40
–
–
–
MAX
+4.6
V
CC
+ 0.3
±20
+125
>1750
>200
>1000
UNIT
V
V
mA
°C
V
V
V
NOTE:
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IR
V
DIFF
T
amb
Supply voltage
Receiver input voltage
Input differential voltage
1
Operating ambient temperature range in free air
V
(CLKinN)–V(CLKin)
PARAMETER
CONDITIONS
MIN
2.25
V
EE
—
–40
MAX
3.8
V
CC
1.00
+85
UNIT
V
V
V
°C
NOTE:
1. To idle an unused differential clock input, connect one input terminal (e.g. CLK1) to V
BB
and leave its complimentary input terminal
(e.g. CLK1) open-circuit, in which case CLK1 will default LOW by its internal pull-down reistor. Inputs should not be shorted to ground or
V
CC.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fan-out and high drive capability products.
2004 Apr 23
4
PCB Design
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