CAT28F020TA-12T datasheet, PDF

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CAT28F020TA-12T: Description2 Megabit CMOS Flash Memory; Categorystorage storage; File Size431KB，15 Pages; ManufacturerCatalyst; Websitehttp://www.catalyst-semiconductor.com/

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CAT28F020TA-12T Overview

2 Megabit CMOS Flash Memory

CAT28F020TA-12T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Catalyst
Parts packaging code	TSOP
package instruction	TSOP1, TSSOP32,.8,20
Contacts	32
Reach Compliance Code	unknow
ECCN code	EAR99
Maximum access time	120 ns
Other features	100000 PROGRAM/ERASE CYCLES; 10 YEARS DATA RETENTION
command user interface	YES
Data polling	NO
Data retention time - minimum	10
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	18.4 mm
memory density	2097152 bi
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	2A
Number of functions	1
Number of terminals	32
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	256KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP32,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
power supply	5 V
Programming voltage	12 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.00001 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
switch bit	NO
type	NOR TYPE
width	8 mm

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CAT28F020

2 Megabit CMOS Flash Memory

Licensed Intel second source

FEATURES

Fast read access time: 90/120 ns

Low power CMOS dissipation:

GEN

ALO

Commercial, industrial and automotive

temperature ranges

Stop timer for program/erase

On-chip address and data latches

JEDEC standard pinouts:

– Active: 30 mA max (CMOS/TTL levels)

– Standby: 1 mA max (TTL levels)

– Standby: 100

A max (CMOS levels)

High speed programming:

– 10

s per byte

– 4 seconds typical chip program

– 32-pin DIP

– 32-pin PLCC

– 32-pin TSOP (8 x 20)

100,000 program/erase cycles

10 year data retention

Electronic signature

0.5 seconds typical chip-erase

12.0V

5% programming and erase voltage

DESCRIPTION

The CAT28F020 is a high speed 256K x 8-bit electrically

erasable and reprogrammable Flash memory ideally

suited for applications requiring in-system or after-sale

code updates. Electrical erasure of the full memory

contents is achieved typically within 0.5 second.

It is pin and Read timing compatible with standard

EPROM and E

PROM devices. Programming and

Erase are performed through an operation and verify

algorithm. The instructions are input via the I/O bus,

using a two write cycle scheme. Address and Data are

latched to free the I/O bus and address bus during the

write operation.

The CAT28F020 is manufactured using Catalyst’s

advanced CMOS floating gate technology. It is designed

to endure 100,000 program/erase cycles and has a data

retention of 10 years. The device is available in JEDEC

approved 32-pin plastic DIP, 32-pin PLCC or 32-pin

TSOP packages.

BLOCK DIAGRAM

I/O0–I/O7

I/O BUFFERS

ERASE VOLTAGE

SWITCH

COMMAND

PROGRAM VOLTAGE

SWITCH

CE, OE LOGIC

DATA

LATCH

SENSE

AMP

ADDRESS LATCH

Y-GATING

Y-DECODER

2,097,152 BIT

MEMORY

ARRAY

5115 FHD F02

A0–A17

X-DECODER

VOLTAGE VERIFY

SWITCH

Characteristics subject to change without notice

Doc. No. 1029, Rev. C

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