PI74SSTVF16857A
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
14-Bit Registered Buffer
Product Features
• Designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I output specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging Options (Lead-free packages are available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor’s PI74SSTVF16857A series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857A universal bus driver is designed
for 2.5V to 2.6V V
DD
operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as V
REF
may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
R
CLK
V
Logic Block Diagram
CLK
CLK
RESET
D1
V
REF
38
39
34
48
35
1
Q1
D
Pericom’s PI74SSTVF16857A is characterized for operation from
0° to 70°C.
Product Pin Configuration
TO 13 OTHER CHANNELS
Product Pin Description
Pin Name
RESET
CLK
CLK
D
Q
GND
V
DD
V
DDQ
V
REF
Description
Reset (Active Low)
Clock Input
Clock Input
Data Input
Data Output
Ground
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-Pin
39
A, K
38
11
37
36
35
34
33
32
31
30
29
28
27
26
25
Truth Table
(1)
Inputs
RESET
L
H
Η
H
CLK
X
↑
↑
L or H
CLK
X
↓
↓
L or H
D
X
H
L
X
Outputs
Q
L
H
L
Q o
( 2 )
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
Notes:
2. Output level before the
1. H = High Signal Level
indicated steady state
L = Low Signal Level
input conditions were
↑
= Transition LOW-to-HIGH
established.
↓
= Transition HIGH-to-LOW
X = Irrelevant
1
PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A
14-Bit Registered Buffer
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Parame te r
Storage Temperature
Supply Voltage
Input Voltage
(1)
Output Voltage
(1,2)
Input Clamp Current
Output Clamp Current
Continuous Output Current
V
DD
, V
DDQ
, or GND current/pin
Package Thermal Impedance
A- Package
K- Package
Symbol
Tstg
V
DD
or V
DDQ
V
I
V
O
I
I K,
V
I <
0
I
O K,
V
O <
0
I
O,
V
O =
0 to V
DDQ
I
DD,
I
DDQ
or GND
Ø
J
A
Ratings
–65 to 150
– 0.5 to 3.6
– 0.5 to V
DD
+ 0.5
– 0.5 to V
DDQ
+ 0.5
– 50
± 50
± 50
±100
70
58
Units
o
C
V
mA
o
C/W
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
O
> V
DDQ
.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A
14-Bit Registered Buffer
Recommended Operating Conditions
Parame te rs
De s cription
PC1600
P C 2700
P C 3200
Reference Voltage V
REF
= 0.5X
V
DDQ
AC input High Voltage
AC input Low Voltage
Input Voltage
DC Input High Voltage
DC Input Low Voltage
Input High Voltage
Input Low Voltage
Common- Mode Input Voltage Range
Peak- to- Peak Input Voltage
High- Level Output Current
Low- Level Output Current
Operating Free- Air Temperature
0
RESET
1. 7
0.7
0.97
0.36
1. 5 3
V
DDQ
+0.6
–16
16
70
mA
ºC
Data Inputs
PC1600
P C 2700
P C 3200
Data Inputs
Data Inputs
0
V
REF
+0.15
V
REF
–0.15
V
REF
M in.
2.3
2.5
1.15
1.25
V
REF
+0.31
V
REF
- 0.31
V
DD
V
Nom.
2.5
2.6
1. 2 5
1.3
M ax.
2.7
2.7
1. 3 5
1. 3 5
Units
V
DD
/V
DDQ
Core/Output Supply Voltage
V
REF
V
IH
V
IL
V
I
V
IH
V
IL
V
IH
V
IL
V
ICR
V
ID
I
OH
I
OL
T
A
CLK,CLK
3
PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A
14-Bit Registered Buffer
DC Electrical Characteristics for PC1600 ~ PC2700
(Over the Operating Range, T
A
= 0°C to +70°C, V
DD
= 2.5V ±200mV, V
DDQ
= 2.5V ±200mV)
Pa ra me te rs
V
IK
V
O H
I
I
= –1 8 mA
Te s t Co nditio ns
V
CC
2.3V
M in.
Typ.
(1)
M ax.
–1.2
Units
I
OH
= –10 0 µA
I
OH
= –8 mA
I
OL
= 10 0 µA
I
OH
= 8mA
V
I
= V
DD
o r GN D
RES ET = GN D
V
I
= V
IH
(AC ) o r V
I
(AC ),
RES ET = V
DD
RES ET = V
DD
V
I
= V
IH (AC )
o r V
IL
(AC ),
C K and C K switching
5 0 % d uty cycle
RES ET = V
DD
V
I
= V
IH (AC )
o r V
IL
(AC ),
C K and C K switching
5 0 % d uty cycle. O ne d ata
inp ut switching at half clo ck
freq uency, 5 0 % d uty cycle
V
I
= V
REF
± 3 10 mV
V
IC R
= 1. 2 5 V, V
I(PP)
= 3 6 0 mV
V
I
= V
C C
o r GN D
2 . 3 V- 2 . 7 V V
DD
–0 . 2 V
2.3V
2 . 3 V- 2 . 7 V
2.3V
2.7V
1.95
0.2
0.35
5
10
25
µA
mA
µA/
clo ck
MHz
V
V
O L
I
I
I
DD
All Inp uts,
S tand b y (S tatic)
O p erating S tatic
Dynamic
O p erating -
C lo ck o nly
I
DDD
Dynamic
O p erating - p er
each d ata inp ut
28
I
O
= 0
2.7V
9
µA/
clo ck
MHz
Data
3.5
3.5
3.5
pF
Data inp uts
C
I
C K and C K
RES ET
2.5
2.5V
2.5
2.5
Notes:
4. Typical values are at V
DD
= Nominal V
DD
, T
A
= +25°C.
4
PS8687
05/27/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74SSTVF16857A
14-Bit Registered Buffer
DC Electrical Characteristics for PC3200
(Over the Operating Range, T
A
= 0°C to +70°C, V
DD
= 2.6V ±100mV, V
DDQ
= 2.6V ±100mV)
Pa ra me te rs
V
IK
V
O H
I
I
= –1 8 mA
Te s t Co nditio ns
V
CC
2.5V
M in.
Typ.
(1)
M ax.
–1.2
Units
I
OH
= –10 0 µA
I
OH
= –8 mA
I
OL
= 10 0 µA
I
OH
= 8mA
V
I
= V
DD
o r GN D
RES ET = GN D
V
I
= V
IH
(AC ) o r V
I
(AC ),
RES ET = V
DD
RES ET = V
DD
V
I
= V
IH (AC )
o r V
IL
(AC ),
C K and C K switching
5 0 % d uty cycle
RES ET = V
DD
V
I
= V
IH (AC )
o r V
IL
(AC ),
C K and C K switching
5 0 % d uty cycle. O ne d ata
inp ut switching at half clo ck
freq uency, 5 0 % d uty cycle
V
I
= V
REF
± 3 10 mV
V
IC R
= 1. 2 5 V, V
I(PP)
= 3 6 0 mV
V
I
= V
C C
o r GN D
2 . 5 V- 2 . 7 V V
DD
–0 . 2 V
2.5V
2 . 5 V- 2 . 7 V
2.5V
2.7V
1.95
0.2
0.35
5
10
25
µA
mA
µA/
clo ck
MHz
V
V
O L
I
I
I
DD
All Inp uts,
S tand b y (S tatic)
O p erating S tatic
Dynamic
O p erating -
C lo ck o nly
I
DDD
Dynamic
O p erating - p er
each d ata inp ut
28
I
O
= 0
2.7V
9
µA/
clo ck
MHz
Data
3.5
3.5
3.5
pF
Data inp uts
C
I
C K and C K
RES ET
2.5
2.6V
2.5
2.5
Notes:
4. Typical values are at V
DD
= Nominal V
DD
, T
A
= +25°C.
5
PS8687
05/27/03
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