SPT7851
10-BIT, 20 MSPS, 79 mW A/D CONVERTER
FEATURES
•
•
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•
•
•
•
•
10-Bit, 20 MSPS Analog-to-Digital Converter
Monolithic CMOS
Internal Track-and-Hold
Low Input Capacitance: 1.4 pF
Low Power Dissipation: 79 mW
2.8 – 3.6 V Power Supply Range
TTL-Compatible Outputs
–40
°C
to +85
°C
Operation
APPLICATIONS
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•
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CCD Imaging Cameras and Sensors
Medical Imaging
RF Communications
Document and Film Scanners
Electro-Optics
Transient Signal Analysis
Handheld Equipment
GENERAL DESCRIPTION
The SPT7851 10-bit, 20 MSPS analog-to-digital converter
has a pipelined converter architecture built in a CMOS pro-
cess. It delivers high performance with a typical power dissi-
pation of only 79 mW. With low distortion and high dynamic
range, this device offers the performance needed for imag-
ing, multimedia, telecommunications and instrumentation
applications.
The SPT7851 is available in a 44-lead Thin Quad Flat Pack
(TQFP) package in the industrial temperature range (–40
°C
to +85
°C).
BLOCK DIAGRAM
ADC
DAC
+
– G=2
D<1…0> Pipeline Stage
VIN+
VIN–
VREF+
VREF–
CLK
Clock
Driver
Digital Delays, Error Correction and Output
10
Stage
1
Stage
2
Stage
9
Stage
10
Digital Output (D0 – D9)
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
V
DD1 ..............................................................................
–0.5 V to +6 V
V
DD2 ..............................................................................
–0.5 V to +6 V
V
DD3 ..............................................................................
–0.5 V to +6 V
Input Voltages
Analog Input .................................
Digital Input ..................................
V
REF
+ ...........................................
V
REF
– ...........................................
CLK ..............................................
Note:
–0.5 V to (V
DD
+0.5 V)
–0.5 V to (V
DD
+0.5 V)
–0.5 V to (V
DD
+0.5 V)
–0.5 V to (V
DD
+0.5 V)
–0.5 V to (V
DD
+0.5 V)
Temperature
Operating Temperature ............................. –40 to +85
°C
Storage Temperature ............................... –65 to +125
°C
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
–T
MAX
, V
DD1
= V
DD2
= V
DD3
=
3.3 V, V
REF
– = 1.0 V, V
REF
+ = 2.0 V, Common Mode Voltage = 1.65 V, ƒ
CLK
= 20 MSPS,
Bias 1 = 90
µA,
Bias 2 = 9.5
µA,
Differential Input, Duty Cycle = 50%, unless otherwise specified.
PARAMETERS
DC Accuracy
Resolution
Differential Linearity
Integral Linearity
No Missing Codes
Analog Input
Input Voltage Range (Differential)
Common Mode Input Voltage
Input Capacitance
Input Bandwidth (Large Signal)
Offset (Mid-scale)
Gain Error
Reference Voltages
Reference Input Voltage Range
(V
REF
+ – V
REF
–)
Negative Reference Voltage (V
REF
–)
Positive Reference Voltage (V
REF
+)
Common Mode Output Voltage (V
CM
)
V
REF
+ Current
V
REF
– Current
Switching Performance
Maximum Conversion Rate
Pipeline Delay
(See Timing Diagram)
Aperture Delay Time (T
AP
)
Aperture Jitter Time
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT7851
TYP
10
±0.6
±0.75
Guaranteed
±0.6
1.2
±1.0
1.65
1.4
120
±1.0
0.3
1.0
1.0
2.0
1.65
35
–25
±1.7
1.9
MAX
UNITS
Bits
LSB
LSB
V
V
VI
IV
IV
V
V
V
V
IV
IV
IV
VI
V
V
VI
IV
V
V
V
IN
+ = V
IN
– = V
CM
V
V
pF
MHz
% FSR
% FSR
V
V
V
V
µA
µA
MHz
Clocks
ns
ps-rms
0.6
0.9
1.9
1.3
1.7
1.3
2.9
1.8
I
O
= –1
µA
20
7.5
5
10
SPT
SPT7851
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8/1/00
ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
–T
MAX
, V
DD1
= V
DD2
= V
DD3
=
3.3 V, V
REF
– = 1.0 V, V
REF
+ = 2.0 V, Common Mode Voltage = 1.65 V, ƒ
CLK
= 20 MSPS,
Bias 1 = 90
µA,
Bias 2 = 9.5
µA,
Differential Input, Duty Cycle = 50%, unless otherwise specified.
PARAMETERS
Dynamic Performance
Effective Number of Bits
ƒ
IN
= 5.0 MHz
ƒ
IN
= 10.0 MHz
Signal-To-Noise Ratio
ƒ
IN
= 5.0 MHz
ƒ
IN
= 10.0 MHz
Total Harmonic Distortion
ƒ
IN
=5.0 MHz
ƒ
IN
=10.0 MHz
Signal-To-Noise and Distortion
ƒ
IN
= 5 MHz
ƒ
IN
= 10 MHz
Spurious Free Dynamic Range
ƒ
IN
= 5.0 MHz
ƒ
IN
= 10.0 MHz
Differential Phase
Differential Gain
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
CLK to Output Delay Time (t
D
)
Power Supply Requirements
Supply Voltages
V
DD1
, V
DD2
, V
DD3
Supply Current
I
DD
Power Dissipation
Power Supply Rejection Ratio (PSRR)
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT7851
TYP
MAX
UNITS
VI
V
VI
V
VI
V
VI
V
VI
V
V
V
VI
VI
VI
VI
V
VI
VI
IV
9.0
9.3
9.0
58
58
–68
–60
–61
Bits
Bits
dB
dB
dB
dB
dB
dB
dB
dB
Degrees
%
57
56
58
56
70
61
0.2
0.5
62
80% V
DD
20% V
DD
±1
±1
1.8
85% V
DD
4
95% V
DD
0.1
8
µA
µA
pF
V
V
ns
V
IN
= GND
V
IN
= V
DD
I
O
= –2 mA
I
O
= +2 mA
0.4
12
IV
VI
VI
V
2.8
3.3
24
79
67
3.6
30
100
V
mA
mW
dB
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions: All parameters having
min/max specifications are guaranteed. The
Test Level column indicates the specific device
testing actually performed during production
and Quality Assurance inspection. Any blank
section in the data column indicates that the
specification is not tested at the specified con-
dition.
TEST LEVEL TEST PROCEDURE
I
II
III
IV
V
VI
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°C,
and sample tested
at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25
°C.
Parameter is
guaranteed over specified temperature range.
SPT
SPT7851
3
8/1/00
TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Input Frequency
80
THD, SNR, SINAD vs Sample Rate
80
THD, SNR, SINAD (dB)
70
70
THD
60
SNR
SINAD
50
THD
SNR
SINAD
THD, SNR, SINAD (dB)
60
THD
SNR
SINAD
50
40
40
30
30
20
100
101
102
20
10 0
101
102
Input Frequency (MHz)
Sample Rate (MSPS)
Note: Bias1 and Bias2 currents optimized for each sample rate.
THD, SNR, SINAD vs Temperature
70
150
Power Dissipation vs Sample Rate
68
THD, SNR, SINAD (dB)
THD
66
Power Dissipation (mW)
125
100
64
75
62
50
60
SNR
58
25
SINAD
56
–40
–25
0
25
50
70
85
0
10 0
101
102
Temperature (°C)
Sample Rate (MSPS)
Note: Bias1 and Bias2 optimized for each sample rate.
Bias 1 Voltage vs Bias 1 Current
3.4
3.2
0.85
3.0
0.90
Bias 2 Voltage vs Bias 2 Current
VBias 2 (V)
VBias1 (V)
0.80
2.8
2.6
2.4
2.2
2.0
0
30
60
90
120
150
180
Bias 1
30
60
90
120
150
VBias 1
2.19
2.53
2.79
3
3.22
0.75
0.70
0.65
0.60
0
3
6
9
IBias 2
3
6
9
12
15
VBias 2
0.6975
0.7535
0.796
0.8295
0.8595
12
15
18
IBias1 (µA)
IBias 2 (µA)
SPT
SPT7851
4
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Figure 1 – Timing Diagram
Sampling Points
N-1
N
N+1
t
AP
A
IN
CLK
N+2
N+6
N+7
N+8
t
D
D
OUT
N-2
N-1
N
GENERAL DESCRIPTION
The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC.
It has a pipelined architecture and incorporates digital error
correction of all 10 bits. This error correction ensures good
linearity performance for input frequencies up to Nyquist.
The inputs are fully differential, making the device insensi-
tive to system-level noise. This device can also be used in a
single-ended mode. (See analog input section.) With the
power dissipation roughly proportional to the sampling rate,
this device is ideal for very low power applications in the
range of 1 to 20 MSPS.
Figure 2 – Typical Interface Circuit
TYPICAL INTERFACE CIRCUIT
The SPT7851 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7851 in
normal circuit operation. The following sections provide a
description of the functions and outline critical performance
criteria to consider for achieving the optimal device perfor-
mance.
+3.3 V
4.7
µF
+
.01
µF
10
µF
+
CLK In
(3 V Logic)
Ref- In
(+1.15 V)
+3.3 V
.01
µF
Ref+ In
(+2.15 V)
+
4.7
µF
.01
µF
11
+3.3 V Digital
0.1
µF
1
GND
CLK
N/C
Decoupling Cap
VDD2
VDD3
VDD1
VRef-
VRef+
VDD1
VDD2
VDD1
12
N/C
N/C
N/C
V
DD3
44
DNC
DNC
D0
D1
(LSB)
90
µA
9.5
µA
.01
µF
(+1.65 V)
GND
Bias1
Bias2
VCM
GND
U1
SPT7851
D2
D3
D4
D5
D6
D7
D9
D8
Interfacing
3 V Logic
RF In
51
68 pF
VIN+
VIN-
22
Minicircuit
T1-6T
GND
GND
34
(MSB)
23
33
AGND
FB
DGND
Note: 1. All V
DD1
, V
DD2
and V
DD3
should be tied together.
2. FB = Ferrite Bead; must be placed as close to U1 as possible.
SPT
SPT7851
5
8/1/00
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