GS8673EQ18BK-550I datasheet, PDF

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GS8673EQ18BK-550I: DescriptionSRAM 1.2/1.5V 4M x 18 72M; Categorystorage; File Size328KB，31 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8673EQ18BK-550I Overview

SRAM 1.2/1.5V 4M x 18 72M

GS8673EQ18BK-550I Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	GSI Technology
Product Category	SRAM
Memory Size	72 Mbit
Organization	4 M x 18
Maximum Clock Frequency	550 MHz
Interface Type	Parallel
Supply Voltage - Max	1.4 V
Supply Voltage - Min	1.25 V
Supply Current - Max	1.93 A
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 100 C
Mounting Style	SMD/SMT
Package / Case	BGA-260
Packaging	Tray
Memory Type	QDR-III
Type	SigmaQuad-IIIe B2
Moisture Sensitive	Yes
Factory Pack Quantity	8

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GS8673EQ18/36BK-675/625/550/500

260-Ball BGA

Commercial Temp

Industrial Temp

Features

• On-Chip ECC with virtually zero SER

• Configurable Read Latency (3.0 or 2.0 cycles)

• Simultaneous Read and Write SigmaQuad-IIIe™ Interface

• Separate I/O Bus

• Double Data Rate interface

• Burst of 2 Read and Write

• Pipelined read operation

• Fully coherent Read and Write pipelines

• 1.35V nominal V

• 1.2V JESD8-16A BIC-3 Compliant Interface

• 1.5V HSTL Interface

• ZQ pin for programmable output drive impedance

• ZT pin for programmable input termination impedance

• Configurable Input Termination

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package

–K: 5/6 RoHS-compliant package

–GK: 6/6 RoHS-compliant package

72Mb SigmaQuad-IIIe™

Burst of 2 ECCRAM™

Clocking and Addressing Schemes

675 MHz–500 MHz

1.35V V

1.2V to 1.5V V

DDQ

The GS8673EQ18/36BK SigmaQuad-IIIe ECCRAMs are

synchronous devices. They employ dual, single-ended master

clocks, CK and CK. These clocks are single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. CK and CK are used to control the address and control

input registers, as well as all output timing.

The KD and KD clocks are dual mesochronous (with respect to

CK and CK) input clocks that are used to control the data input

registers. Consequently, data input setup and hold windows

can be optimized independently of address and control input

setup and hold windows.

Each internal read and write operation in a SigmaQuad-IIIe B2

ECCRAM is two times wider than the device I/O bus. An input

data bus de-multiplexer is used to accumulate incoming data

before it is simultaneously written to the memory array. An

output data multiplexer is used to capture the data produced

from a single memory array read and then route it to the

appropriate output drivers as needed. Therefore, the address

field of a SigmaQuad-IIIe B2 ECCRAM is always one address

pin less than the advertised index depth (e.g. the 4M x 18 has

2M addressable index).

SigmaQuad-IIIe™ Family Overview

SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the

SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance

ECCRAMs. Although very similar to GSI's second generation

of networking SRAMs (the SigmaQuad-II/SigmaDDR-II

family), these third generation devices offer several new

features that help enable significantly higher performance.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles, etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

Parameter Synopsis

Speed Bin

-675

-625

-550

-500

Operating Frequency

675 / 450 MHz

625 / 400 MHz

550 / 375 MHz

500 / 333 MHz

Data Rate (per pin)

1350 / 900 Mbps

1250 / 800 Mbps

1100 / 750 Mbps

1000 / 666 Mbps

Read Latency

3.0 / 2.0

1.3V to 1.4V

1.25V to 1.4V

Note: Please contact GSI for availability of 714 MHz devices.

Rev: 1.07 12/2017

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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