EEWORLDEEWORLDEEWORLD

Part Number

Search

GS81314PQ37GK-800I

Description
SRAM 1.2/1.25V 4M x 36 144M
Categorystorage   
File Size261KB,39 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

GS81314PQ37GK-800I Overview

SRAM 1.2/1.25V 4M x 36 144M

GS81314PQ37GK-800I Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerGSI Technology
Product CategorySRAM
RoHSDetails
Memory Size144 Mbit
Organization4 M x 36
Maximum Clock Frequency800 MHz
Interface TypeParallel
Supply Voltage - Max1.35 V
Supply Voltage - Min1.15 V
Supply Current - Max2.7 A
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 100 C
Mounting StyleSMD/SMT
Package / CaseBGA-260
PackagingTray
Memory TypeQDR-IV
TypeSigmaQuad-IVe B2
Moisture SensitiveYes
Factory Pack Quantity10
GS81314PQ19/37GK-933/800
260-Pin BGA
Com & Ind Temp
POD I/O
Features
4Mb x 36 and 8Mb x 18 organizations available
Organized as a single logical memory bank
933 MHz maximum operating frequency
1.866 BT/s peak transaction rate (in billions per second)
134 Gb/s peak data bandwidth (in x36 devices)
Separate I/O DDR Data Buses
Non-multiplexed DDR Address Bus
Two operations - Read and Write - per clock cycle
No address/bank restrictions on Read and Write ops
Burst of 2 Read and Write operations
5 cycle Read Latency
On-chip ECC with virtually zero SER
Loopback signal timing training capability
1.2V ~ 1.3V nominal core voltage
1.2V ~ 1.3V POD I/O interface
Configuration registers
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
144Mb SigmaQuad-IVe™
Burst of 2 Single-Bank ECCRAM™
Clocking and Addressing Schemes
Up to 933 MHz
1.2V ~ 1.3V V
DD
1.2V ~ 1.3V V
DDQ
The GS81314PQ19/37GK SigmaQuad-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
SigmaQuad-IVe™ Family Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Parameter Synopsis
Speed Grade
-933
-800
Max Operating Frequency
933 MHz
800 MHz
Read Latency
5 cycles
5 cycles
V
DD
1.25V to 1.35V
1.15V to 1.35V
Rev: 1.02 3/2016
1/39
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS81314PQ37GK-800I Related Products

GS81314PQ37GK-800I GS81314PQ19GK-933 GS81314PQ19GK-800 GS81314PQ19GK-933I GS81314PQ19GK-800I GS81314PQ37GK-800 GS81314PQ37GK-933I GS81314PQ37GK-933
Description SRAM 1.2/1.25V 4M x 36 144M SRAM 1.2/1.25V 8M x 18 144M SRAM 1.2/1.25V 8M x 18 144M SRAM 1.2/1.25V 8M x 18 144M Static random access memory 1.2/1.25V 8M x 18 144M Static random access memory 1.2/1.25V 4M x 36 144M Static random access memory 1.2/1.25V 4M x 36 144M Static random access memory 1.2/1.25V 4M x 36 144M
Maker - GSI Technology - GSI Technology GSI Technology GSI Technology GSI Technology GSI Technology
organize - 8MX18 - 8MX18 8 M x 18 4 M x 36 4MX36 4MX36
Monthly Original Selection March 2018 (No. 2)
[size=4][color=#ff0000]Activity time[/color]: March 1 - March 31, 2018 (one issue per month, revised issue 2)[/size] [size=4][color=#0000ff]Selection scope[/color]: DIY example posts, technical knowle...
okhxyyo Suggestions & Announcements
Brother Aniu's series of stories: the five little fortunes changed jobs
Brother Niu went to the park for a walk on the day of the Dragon Head Raising on February 2. It was a beautiful spring day with a gentle breeze and a gentle breeze. There were many bald old men walkin...
jameswangsynnex Talking
How to deal with redundant input terminals of CMOS and TTL integrated gate circuits?
[size=4] CMOS and TTL integrated gate circuits often encounter such a problem in actual use, that is, there are redundant input terminals. How to correctly handle these redundant input terminals to ma...
Aguilera Analogue and Mixed Signal
Drawings for amplified sound-powered telephone
Device name: Marine acoustic telephone (amplified type) Origin: Japan Manufacturer: OKI Circuit diagram:Dedicated low-voltage voice transmission chip: PBL3726_6 [[i] This post was last edited by zcgza...
zcgzanne Industrial Control Electronics
Independent buttons
One end of the independent button is connected to the I/O port of 430, and the other end is grounded. But every time after running P1DIR &=~BIT0, if the button is not pressed, the BIT0 position in PIN...
zzbaizhi Microcontroller MCU
Has anyone worked with DDRAM? What does pre-charging mean?
I recently wanted to write a driver for DDRAM, so I looked at the datasheet, but there are some concepts that I am not very clear about. First of all, there are many instructions about charging in the...
sglhero FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2280  491  959  426  1779  46  10  20  9  36 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号