GS81314PQ19/37GK-933/800
260-Pin BGA
Com & Ind Temp
POD I/O
Features
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•
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4Mb x 36 and 8Mb x 18 organizations available
Organized as a single logical memory bank
933 MHz maximum operating frequency
1.866 BT/s peak transaction rate (in billions per second)
134 Gb/s peak data bandwidth (in x36 devices)
Separate I/O DDR Data Buses
Non-multiplexed DDR Address Bus
Two operations - Read and Write - per clock cycle
No address/bank restrictions on Read and Write ops
Burst of 2 Read and Write operations
5 cycle Read Latency
On-chip ECC with virtually zero SER
Loopback signal timing training capability
1.2V ~ 1.3V nominal core voltage
1.2V ~ 1.3V POD I/O interface
Configuration registers
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
144Mb SigmaQuad-IVe™
Burst of 2 Single-Bank ECCRAM™
Clocking and Addressing Schemes
Up to 933 MHz
1.2V ~ 1.3V V
DD
1.2V ~ 1.3V V
DDQ
The GS81314PQ19/37GK SigmaQuad-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
SigmaQuad-IVe™ Family Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Parameter Synopsis
Speed Grade
-933
-800
Max Operating Frequency
933 MHz
800 MHz
Read Latency
5 cycles
5 cycles
V
DD
1.25V to 1.35V
1.15V to 1.35V
Rev: 1.02 3/2016
1/39
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PQ19/37GK-933/800
8M x 18 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCH
(CFG)
MCL
(B4M)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
Q17
V
SS
Q16
V
SS
Q15
Q14
V
SS
CQ1
CQ1
V
SS
NU
O
NU
O
V
SS
NU
O
V
SS
NU
O
V
SS
V
DD
2
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
V
SS
Q13
V
DDQ
Q12
Q11
V
DDQ
Q10
V
DDQ
Q9
QINV1
3
V
DD
V
SS
D17
V
SS
D16
V
SS
D15
D14
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
NU
I
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
ss
D13
V
DDQ
D12
D11
V
DD
D10
V
DDQ
D9
DINV1
9
PZT1
PZT0
V
SS
SA20
V
SS
SA18
V
SS
SA16
V
SS
KD0
KD0
V
SS
MCL
V
SS
RST
V
SS
NC
(1152 Mb)
10
DINV0
D0
V
DDQ
D1
V
DD
D2
D3
V
DDQ
D4
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
NU
I
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
D5
D6
V
SS
D7
V
SS
D8
V
SS
V
DD
12
QINV0
Q0
V
DDQ
Q1
V
DDQ
Q2
Q3
V
DDQ
Q4
V
DDQ
V
SS
NU
O
V
DDQ
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
NU
O
NU
O
13
V
DD
V
SS
NU
O
V
SS
NU
O
V
SS
NU
O
NU
O
V
SS
CQ0
CQ0
V
SS
Q5
Q6
V
SS
Q7
V
SS
Q8
V
SS
V
DD
MRW
NC
(RSVD)
ZQ
MCH
(SIOM)
MCL
V
SS
SA19
V
SS
SA17
V
SS
SA15
V
SS
KD1
KD1
V
SS
PLL
V
SS
MCH
V
SS
NC
(576 Mb)
SA13
V
DDQ
SA11
V
DD
SA9
V
DDQ
SA7
V
DD
V
DDQ
SA5
V
DDQ
SA3
V
DD
SA1
V
DDQ
SA21
(x18)
V
DD
NC
(288 Mb)
SA14
V
DDQ
SA12
V
DD
SA10
V
DDQ
SA8
V
DD
V
DDQ
SA6
V
DDQ
SA4
V
DD
SA2
V
DDQ
SA0
(B2)
V
SS
V
DDQ
NU
I
W
V
SS
CK
CK
V
SS
R
MZT
V
DDQ
V
SS
NC
(RSVD)
V
SS
TCK
TDO
V
DD
RCS
NC
(RSVD)
V
SS
TMS
TDI
MCL
NU
MCL
MCL
Notes:
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.02 3/2016
2/39
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PQ19/37GK-933/800
4M x 36 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCL
(CFG)
MCL
(B4M)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
Q26
V
SS
Q25
V
SS
Q24
Q23
V
SS
CQ1
CQ1
V
SS
Q30
Q29
V
SS
Q28
V
SS
Q27
V
SS
V
DD
2
QINV3
Q35
V
DDQ
Q34
V
DDQ
Q33
Q32
V
DDQ
Q31
V
DDQ
V
SS
Q22
V
DDQ
Q21
Q20
V
DDQ
Q19
V
DDQ
Q18
QINV2
3
V
DD
V
SS
D26
V
SS
D25
V
SS
D24
D23
V
SS
V
REF
QVLD1
4
DINV3
D35
V
DDQ
D34
V
DD
D33
D32
V
DDQ
D31
V
DD
V
SS
D22
V
DDQ
D21
D20
V
DD
D19
V
DDQ
D18
DINV2
9
PZT1
PZT0
V
SS
SA20
V
SS
SA18
V
SS
SA16
V
SS
KD0
KD0
V
SS
MCL
V
SS
RST
V
SS
NC
(1152 Mb)
10
DINV0
D0
V
DDQ
D1
V
DD
D2
D3
V
DDQ
D4
V
DD
V
SS
D13
V
DDQ
D14
D15
V
DD
D16
V
DDQ
D17
DINV1
11
V
DD
V
SS
D9
V
SS
D10
V
SS
D11
D12
V
SS
V
REF
QVLD0
V
SS
D5
D6
V
SS
D7
V
SS
D8
V
SS
V
DD
12
QINV0
Q0
V
DDQ
Q1
V
DDQ
Q2
Q3
V
DDQ
Q4
V
DDQ
V
SS
Q13
V
DDQ
Q14
Q15
V
DDQ
Q16
V
DDQ
Q17
QINV1
13
V
DD
V
SS
Q9
V
SS
Q10
V
SS
Q11
Q12
V
SS
CQ0
CQ0
V
SS
Q5
Q6
V
SS
Q7
V
SS
Q8
V
SS
V
DD
MRW
NC
(RSVD)
ZQ
MCH
(SIOM)
MCL
V
SS
SA19
V
SS
SA17
V
SS
SA15
V
SS
KD1
KD1
V
SS
PLL
V
SS
MCH
V
SS
NC
(576 Mb)
SA13
V
DDQ
SA11
V
DD
SA9
V
DDQ
SA7
V
DD
V
DDQ
SA5
V
DDQ
SA3
V
DD
SA1
V
DDQ
NU
I
(x18)
V
DD
NC
(288 Mb)
SA14
V
DDQ
SA12
V
DD
SA10
V
DDQ
SA8
V
DD
V
DDQ
SA6
V
DDQ
SA4
V
DD
SA2
V
DDQ
SA0
(B2)
V
SS
V
DDQ
NU
I
W
V
SS
CK
CK
V
SS
R
MZT
V
DDQ
V
SS
NC
(RSVD)
V
SS
D30
D29
V
SS
D28
V
SS
D27
V
SS
V
DD
V
SS
TCK
TDO
V
DD
RCS
NC
(RSVD)
V
SS
TMS
TDI
MCL
NU
MCL
MCL
Notes:
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven High.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.02 3/2016
3/39
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PQ19/37GK-933/800
Pin Description
Symbol
SA[21:0]
D[35:0]
Description
Address
— Read address is registered on
CK
and write address is registered on
CK.
Write Data
— Registered on
KD
and
KD
during Write operations.
D[17:0] - x18 and x36.
D[35:18] - x36 only.
Write Data Inversion
— Registered on
KD
and
KD
(along with write data) during Write operations.
Indicate if the associated write data byte is inverted (DINVx = 1) or not (DINVx = 0).
DINV0 - associated with D[8:0] in x18 and x36.
DINV1 - associated with D[17:9] in x18 and x36.
DINV2 - associated with D[26:18] in x36 only.
DINV3 - associated with D[35:27] in x36 only.
Note:
Treated as NU inputs when Data Inversion is disabled.
Read Data
— Aligned with
CQ
and
CQ
during Read operations.
Q[17:0] - x18 and x36.
Q[35:18] - x36 only.
Read Data Inversion
— Aligned with
CQ
and
CQ
(along with read data) during Read operations.
Indicate if the associated read data byte is inverted (QINVx = 1) or not (QINVx = 0).
QINV0 - associated with Q[8:0] in x18 and x36.
QINV1 - associated with Q[17:9] in x18 and x36.
QINV2 - associated with Q[26:18] in x36 only.
QINV3 - associated with Q[35:27] in x36 only.
Note:
Treated as NU outputs when Data Inversion is disabled.
Read Data Valid
— Driven high one half cycle before valid read data.
Primary Input Clocks
— Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks
— Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch D[17:0], DINV[1:0] in x36, and D[8:0], DINV0 in x18.
KD1, KD1: latch D[35:18], DINV[3:2] in x36, and D[17:9], DINV1 in x18.
Read Data Output Clocks
— Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with Q[17:0], QINV[1:0] in x36, and Q[8:0], QINV0 in x18.
CQ1, CQ1: align with Q[35:18], QINV[3:2] in x36, and Q[17:9], QINV1 in x18.
Read Enable
— Registered on
CK.
See the Clock Truth Table for functionality.
Write Enable
— Registered on
CK.
See the Clock Truth Table for functionality.
Mode Register Write
— Registered onCK. Can be used synchronously or asynchronously to enable Reg-
ister Write Mode. See the State and Clock Truth Tables for functionality.
PLL Enable
— Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Reset
— Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Type
Input
Input
DINV[3:0]
Input
Q[35:0]
Output
QINV[3:0]
Output
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
Output
Input
Input
CQ[1:0],
CQ[1:0]
R
W
MRW
Output
Input
Input
Input
PLL
Input
RST
Input
Rev: 1.02 3/2016
4/39
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS81314PQ19/37GK-933/800
Symbol
ZQ
RCS
Description
Driver / ODT Impedance Control Resistor Input
— Must be connected to V
SS
through an external resistor
RQ to program driver and ODT impedances.
Current Source Resistor Input
— Must be connected to V
SS
through an external 2K resistor to provide
an accurate current source for the PLL.
ODT Mode Select
— Sets the default ODT state globally for all input groups during power-up and reset.
Must be tied High or Low.
MZT = 0: disables ODT on all input groups, regardless of PZT[1:0].
MZT = 1: enables ODT on select input groups, as specified by PZT[1:0].
Note:
The ODT state for each input group can be changed at any time via the Configuration Registers.
ODT Configuration Select
— Set the default ODT state for various combinations of input groups during
power-up and reset, when MZT = 1. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Note:
The ODT state for each input group can be changed at any time via the Configuration Registers.
Core Power Supply
I/O Power Supply
Input Reference Voltage
— Input buffer reference voltage.
Ground
JTAG Clock
— Weakly pulled Low internally.
JTAG Mode Select
— Weakly pulled High internally.
JTAG Data Input
— Weakly pulled High internally.
JTAG Data Output
Must Connect High
— May be tied to V
DDQ
directly or via a 1k resistor.
Must Connect Low
— May be tied to V
SS
directly or via a 1k resistor.
No Connect
— There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input
— There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled High internally. They may be left unconnected or tied/driven High. They should not
be tied/driven Low.
Not Used Output
— There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
Type
Input
Input
MZT
Input
PZT[1:0]
Input
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
MCH
MCL
NC
—
—
—
—
Input
Input
Input
Output
Input
Input
—
NU
I
NU
O
Input
Output
Rev: 1.02 3/2016
5/39
© 2015, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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