K7P801811B datasheet, PDF - EEWORLD Datasheet

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K7P801811B: Description256Kx36 & 512Kx18 Synchronous Pipelined SRAM; File Size248KB，13 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7P801811B Overview

256Kx36 & 512Kx18 Synchronous Pipelined SRAM

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K7P803611B

K7P801811B

Document Title

Preliminary

256Kx36 & 512Kx18 SRAM

256Kx36 & 512Kx18 Synchronous Pipelined SRAM

Revision History

Rev. No.

Rev. 0.0

Rev. 1.0

Rev. 2.0

Rev. 3.0

Rev. 4.0

History

- Initial Document.

- Final specification release

- Absolute Maximum Rating VDDQ changed from 2.825V to 2.4V.

- Function Description modified

- Add -HC27 part (Part Number, Idd, AC Characteristics)

Draft Date

Feb. 2001

May. 2001

Jan. 2002

Mar. 2002

Aug. 2002

Remark

Preliminary

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.

-1-

Aug. 2002

Rev 4.0

K7P803611B

K7P801811B

FUNCTION DESCRIPTION

Preliminary

256Kx36 & 512Kx18 SRAM

The K7P803611B and K7P801811B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as

262,144 words by 36 bits for K7P803611B and 524,288 words by 18 bits for K7P801811B, fabricated using Samsung's advanced

CMOS technology.

Single differential HSTL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising

edge of K clock, Addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from

output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after addresses

and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.

Read Operation

During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is

read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock.

During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This

characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-

ple SRAM cycles to perform a single read operation.

Write Operation(Late Write)

During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the

following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and

only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the

timing of SW[a:d] is the same as the SW signal.

Bypass Read Operation

Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are

identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to

byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass

read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM arry.

Sleep Mode

Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored

and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep

mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all

pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-

tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.

Mode Control

There are two mode control select pins (M

and M

) used to set the proper read protocol. This SRAM supports single clock pipelined

operating mode. For proper specified device operation, M

must be connected to V

and M

must be connected to V

DDQ

. These

mode pins must be set at power-up and must not change during device operation.

Programmable Impedance Output Driver

The data output driver impedance is adjusted by an external resistor, RQ, connected between ZQ pin and V

, and is equal to RQ/5.

For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by test(10% by design)

and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that

do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance

updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Imped-

ance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and

proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles

have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up

requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-

read cycles. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to V

or V

DDQ

Power-Up/Power-Down Supply Voltage Sequencing

The following power-up supply voltage application is recommended: V

, V

DDQ

, V

REF

, then V

. V

and V

DDQ

can be applied

simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-up. The following power-down supply voltage

removal sequence is recommended: V

, V

REF

, V

DDQ

, V

. V

and V

DDQ

can be removed simultaneously, as long as V

DDQ

does not exceed V

by more than 0.5V during power-down.

-4-

Aug. 2002

Rev 4.0

K7P801811B Related Products

	K7P801811B	K7P803611B-HC30	K7P803611B	K7P803611B-HC33	K7P803611B-HC25	K7P803611B-HC27	K7P801811B-HC27	K7P801811B-HC33	K7P801811B-HC30	K7P801811B-HC25
Description	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM	256Kx36 & 512Kx18 Synchronous Pipelined SRAM
Is it Rohs certified?	-	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	-	SAMSUNG	-	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	-	BGA	-	BGA	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	-	BGA, BGA119,7X17,50	-	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50	BGA, BGA119,7X17,50
Contacts	-	119	-	119	119	119	119	119	119	119
Reach Compliance Code	-	compli	-	compli	compliant	compli	compli	compli	compli	compli
ECCN code	-	3A991.B.2.A	-	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	-	1.6 ns	-	1.5 ns	2 ns	1.85 ns	1.85 ns	1.5 ns	1.6 ns	2 ns
Other features	-	PIPELINED ARCHITECTURE	-	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
I/O type	-	COMMON	-	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	-	R-PBGA-B119	-	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119	R-PBGA-B119
JESD-609 code	-	e0	-	e0	e0	e0	e0	e0	e0	e0
length	-	22 mm	-	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm	22 mm
memory density	-	9437184 bi	-	9437184 bi	9437184 bit	9437184 bi	9437184 bi	9437184 bi	9437184 bi	9437184 bi
Memory IC Type	-	STANDARD SRAM	-	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM	STANDARD SRAM
memory width	-	36	-	36	36	36	18	18	18	18
Number of functions	-	1	-	1	1	1	1	1	1	1
Number of terminals	-	119	-	119	119	119	119	119	119	119
word count	-	262144 words	-	262144 words	262144 words	262144 words	524288 words	524288 words	524288 words	524288 words
character code	-	256000	-	256000	256000	256000	512000	512000	512000	512000
Operating mode	-	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	-	70 °C	-	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	-	256KX36	-	256KX36	256KX36	256KX36	512KX18	512KX18	512KX18	512KX18
Output characteristics	-	3-STATE	-	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	-	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	BGA	-	BGA	BGA	BGA	BGA	BGA	BGA	BGA
Encapsulate equivalent code	-	BGA119,7X17,50	-	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50	BGA119,7X17,50
Package shape	-	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	-	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	-	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	-	1.5,3.3 V	-	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V	1.5,3.3 V
Certification status	-	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum standby current	-	0.07 A	-	0.07 A	0.07 A	0.07 A	0.07 A	0.07 A	0.07 A	0.07 A
Minimum standby current	-	3.15 V	-	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Maximum slew rate	-	0.62 mA	-	0.7 mA	0.55 mA	0.58 mA	0.53 mA	0.65 mA	0.57 mA	0.5 mA
Maximum supply voltage (Vsup)	-	3.45 V	-	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	-	3.15 V	-	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	-	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	-	YES	-	YES	YES	YES	YES	YES	YES	YES
technology	-	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	-	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	-	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	BALL	-	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	-	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	-	BOTTOM	-	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	-	14 mm	-	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm	14 mm

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