K7P803611B
K7P801811B
FEATURES
• 256Kx36 or 512Kx18 Organizations.
• 3.3V V
DD
/1.5V V
DDQ
(2.0V max V
DDQ
).
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1).
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
Preliminary
256Kx36 & 512Kx18 SRAM
256Kx36 & 512Kx18 Synchronous Pipelined SRAM
Organization
Part Number
K7P803611B-HC33
256Kx36
K7P803611B-HC30
K7P803611B-HC27
K7P803611B-HC25
K7P801811B-HC33
512Kx18
K7P801811B-HC30
K7P801811B-HC27
K7P801811B-HC25
Maximum
Frequency
333MHz
300MHz
250MHz
250MHz
333MHz
300MHz
300MHz
250MHz
Access
Time
1.5
1.6
1.85
2.0
1.5
1.6
1.85
2.0
FUNCTIONAL BLOCK DIAGRAM
SA[0:17]
or [0:18]
Clock
Buffer
Write
Address
Register
18 or 19
18 or 19
Read
Address
Register
2:1
MUX
Dec.
Data Out
36 or 18
S/A Array
36 or 18
36 or 18
MUX0
36 or 18
WAY
SS
SW
ZZ
G
Internal
Clock
Generator
OE
36 or 18
Control
Register
Control
Logic
E
Data In
Register
(2 stage)
36 or 18
Memory Array
256Kx36
512Kx18
K,K
Data In
36 or 18
W/D
Array
Data Out
Register
36 or 18
36 or 18
XDIN
DQ
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SS
SW
SWa
SWb
SWc
SWd
M
1
, M
2
G
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Select
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Read Protocol Mode Pins (M
1
=V
SS
, M
2
=V
DDQ
)
Asynchronous Output Enable
Pin Name
ZZ
ZQ
TCK
TMS
TDI
TDO
V
REF
V
DD
V
DDQ
V
SS
NC
Pin Description
Asynchronous Power Down
Output Driver Impedance Control
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
Aug. 2002
Rev 4.0
-2-
K7P803611B
K7P801811B
FUNCTION DESCRIPTION
Preliminary
256Kx36 & 512Kx18 SRAM
The K7P803611B and K7P801811B are 9,437,184 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
262,144 words by 36 bits for K7P803611B and 524,288 words by 18 bits for K7P801811B, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level K clocks are used to initiate read/write operation and all internal operations are self-timed. At the rising
edge of K clock, Addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are updated from
output registers at the next rising edge of K clock. An internal write data buffer allows write data to follow one cycle after addresses
and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is
read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock.
During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write Operation(Late Write)
During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the
following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and
only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the
timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to
byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass
read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM arry.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-
tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
Mode Control
There are two mode control select pins (M
1
and M
2
) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M
1
must be connected to V
SS
and M
2
must be connected to V
DDQ
. These
mode pins must be set at power-up and must not change during device operation.
Programmable Impedance Output Driver
The data output driver impedance is adjusted by an external resistor, RQ, connected between ZQ pin and V
SS
, and is equal to RQ/5.
For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by test(10% by design)
and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates occur early in cycles that
do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In all cases impedance
updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. Imped-
ance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is selected or not and
proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 continuous read cycles
have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are no power up
requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-
read cycles. The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to V
SS
or V
DDQ
.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
-4-
Aug. 2002
Rev 4.0
K7P803611B
K7P801811B
TRUTH TABLE
K
X
X
↑
↑
↑
↑
↑
↑
↑
↑
ZZ
H
L
L
L
L
L
L
L
L
L
G
X
H
L
L
X
X
X
X
X
X
SS
X
X
H
L
L
L
L
L
L
L
SW
X
X
X
H
L
L
L
L
L
L
SWa
X
X
X
X
H
L
H
H
H
L
SWb
X
X
X
X
H
H
L
H
H
L
SWc
X
X
X
X
H
H
H
L
H
L
SWd
X
X
X
X
H
H
H
H
L
L
DQa
Hi-Z
Hi-Z
Hi-Z
Preliminary
256Kx36 & 512Kx18 SRAM
DQb
Hi-Z
Hi-Z
Hi-Z
DQc
Hi-Z
Hi-Z
Hi-Z
DQd
Hi-Z
Hi-Z
Hi-Z
Operation
Power Down Mode. No Operation
Output Disabled.
Output Disabled. No Operation
D
OUT
D
OUT
D
OUT
D
OUT
Read Cycle
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
D
IN
Hi-Z
Hi-Z
D
IN
Hi-Z
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
D
IN
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D
IN
D
IN
No Bytes Written
Write first byte
Write second byte
Write third byte
Write fourth byte
Write all bytes
NOTE
: K & K are complementary
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to V
SS
Output Supply Voltage Relative to V
SS
Voltage on any pin Relative to V
SS
Output Short-Circuit Current(per I/O)
Storage Temperature
Symbol
V
DD
V
DDQ
V
IN
I
OUT
T
STR
Value
-0.5 to 3.9
-0.5 to 2.4
-0.5 to V
DDQ
+0.5 (2.4V
MAX
)
25
-55 to 125
Unit
V
V
V
mA
°C
NOTE
: Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.
Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Input Low Level
Input Reference Voltage
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
REF
V
IN
-CLK
V
DIF
-CLK
V
CM
-CLK
Min
3.15
1.4
V
REF
+0.1
-0.3
0.68
-0.3
0.1
0.68
Typ
3.3
1.5
-
-
0.75
-
-
0.75
Max
3.45
2.0
V
DDQ
+0.3
V
REF
-0.1
1.0
V
DDQ
+0.3
V
DDQ
+0.3
1.0
Unit
V
V
V
V
V
V
V
V
Note
-5-
Aug. 2002
Rev 4.0
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