MPC9239EI datasheet, PDF - EEWORLD Datasheet

MPC9239EI: Description900 MHz Low Voltage LVPECL Clock Synthesizer; File Size345KB，14 Pages; ManufacturerFREESCALE (NXP)

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MPC9239EI Overview

900 MHz Low Voltage LVPECL Clock Synthesizer

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Freescale Semiconductor

Technical Data

MPC9239

Rev. 3, 08/2005

900 MHz Low Voltage LVPECL

Clock Synthesizer

The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted for

high performance clock generation in mid-range to high-performance telecom,

networking, and computing applications. With output frequencies from

3.125 MHz to 900 MHz and the support of differential LVPECL output signals the

device meets the needs of the most demanding clock applications.

Features

•

3.125 MHz to 900 MHz synthesized clock output signal

Differential LVPECL output

LVCMOS compatible control inputs

On-chip crystal oscillator for reference frequency generation

Alternative LVCMOS compatible reference input

3.3 V power supply

Fully integrated PLL

Minimal frequency overshoot

Serial 3-wire programming interface

Parallel programming interface for power-up

28 PLCC and 32 LQFP packaging

28-lead and 32-lead Pb-free package available

SiGe Technology

Ambient temperature range 0°C to + 70°C

Pin and function compatible to the MC12439

MPC9239

900 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

FN SUFFIX

28-LEAD PLCC PACKAGE

CASE 776-02

EI SUFFIX

28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE

CASE 776-02

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-04

Functional Description

The internal crystal oscillator uses the external quartz crystal as the basis of

its frequency reference. The frequency of the internal crystal oscillator or external

reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is

scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency f

XTAL

, the PLL

feedback-divider M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency

by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase

lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value

must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division

ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven

differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50

Ω

to V

– 2.0 V. The

positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize

noise induced jitter.

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]

inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes

valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the

serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control

inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the

S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this

document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input.

Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled

by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the

TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the f

OUT

by 16. The power down sequence is

clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of

the PWR_DOWN pin, the f

OUT

input will step back up to its programmed frequency in four discrete increments.

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