Freescale Semiconductor
Technical Data
MPC9239
Rev. 3, 08/2005
900 MHz Low Voltage LVPECL
Clock Synthesizer
The MPC9239 is a 3.3 V compatible, PLL based clock synthesizer targeted for
high performance clock generation in mid-range to high-performance telecom,
networking, and computing applications. With output frequencies from
3.125 MHz to 900 MHz and the support of differential LVPECL output signals the
device meets the needs of the most demanding clock applications.
Features
•
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•
•
•
•
•
•
•
•
•
•
•
•
•
3.125 MHz to 900 MHz synthesized clock output signal
Differential LVPECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference input
3.3 V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
28 PLCC and 32 LQFP packaging
28-lead and 32-lead Pb-free package available
SiGe Technology
Ambient temperature range 0°C to + 70°C
Pin and function compatible to the MC12439
MPC9239
900 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
EI SUFFIX
28-LEAD PLCC PACKAGE
Pb-FREE PACKAGE
CASE 776-02
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of
its frequency reference. The frequency of the internal crystal oscillator or external
reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1800 MHz. Its output is
scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency f
XTAL
, the PLL
feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50
Ω
to V
CC
– 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this
document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input.
Refer to the programming section for more information. The TEST output reflects various internal node values, and is controlled
by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the
TEST output. The PWR_DOWN pin, when asserted, will synchronously divide the f
OUT
by 16. The power down sequence is
clocked by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de-assertion of
the PWR_DOWN pin, the f
OUT
input will step back up to its programmed frequency in four discrete increments.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
XTAL_IN
XTAL_OUT
f
REF_EXT
XTAL
10 – 20 MHz
1
÷2
0
Ref
VCO
÷2
PLL
800 – 1800 MHz
FB
÷0
TO
÷127
7-BIT M-DIVIDER
÷2
÷1
÷2
÷4
÷8
11
00
01
10
÷16
1
OE
0
f
OUT
f
OUT
V
CC
XTAL_SEL
V
CC
P_LOAD
S_LOAD
LE
P/S
TEST
2
N-LATCH
3
T-LATCH
TEST
9
M-LATCH
0
S_DATA
S_CLOCK
BITS 11-5
V
CC
1
BITS 3-4
0
1
BITS 0-2
12-BIT SHIFT REGISTER
M[0:6]
N[1:0]
PWR_DOWN
OE
Figure 1. MPC9239 Logic Diagram
XTAL_SEL
M[6]
M[5]
18
TEST
GND
S_CLOCK
S_DATA
S_LOAD
V
CC_PLL
PWR_DOWN
f
REF_EXT
XTAL_IN
2
6
2
7
2
8
1
2
3
4
25
24
23
22
21
20
GND
f
OUT
V
CC
f
OUT
V
CC
19
18
17
16
N[1]
N[0]
NC
XTAL_SEL
M[6]
M[5]
M[4]
24
GND
TEST
V
CC
V
CC
GND
f
OUT
f
OUT
V
CC
25
26
27
28
29
30
31
32
1
23
22
21
20
19
M[4]
17
16
15
14
NC
M[3]
M[2]
M[1]
M[0]
P_LOAD
OE
XTAL_OUT
13
12
11
10
9
8
XTAL_IN
N[1]
N[0]
3
NC
MPC9239
15
14
13
12
MPC9239
5
XTAL_OUT
6
OE
7
P_LOAD
8
M[0]
9
M[1]
10
M[2]
11
M[3]
2
NC
4
5
6
7
S_CLOCK
S_DATA
PWR_DOWN
S_LOAD
V
CC_PLL
V
CC_PLL
Figure 2. MPC9239 28-Lead PLCC Pinout
(Top View)
Figure 3. MPC9239 32-Lead LQFP Pinout
(Top View)
MPC9239
2
Advanced Clock Drivers Devices
Freescale Semiconductor
f
REF_EXT
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
f
REF_EXT
f
OUT
, f
OUT
TEST
XTAL_SEL
PWR_DOWN
Input
Output
Output
Input
Input
1
0
0
I/O
Default
Type
Analog
LVCMOS
LVPECL
LVCMOS
LVCMOS
LVCMOS
Crystal oscillator interface.
Alternative PLL reference input.
Differential clock output.
Test and device diagnosis output.
PLL reference select input.
Configuration input for power down mode. Assertion (deassertion) of power down
will decrease (increase) the output frequency by a ratio of 16 in 4 discrete steps.
PWR_DOWN assertion (deassertion) is synchronous to the input reference clock.
Serial configuration control input. This inputs controls the loading of the
configuration latches with the contents of the shift register. The latches will be
transparent when this signal is high, thus the data must be stable on the high-to-low
transition.
Parallel configuration control input. this input controls the loading of the
configuration latches with the content of the parallel inputs (M and N). The latches
will be transparent when this signal is low, thus the parallel data must be stable on
the low-to-high transition of P_LOAD. P_LOAD is state sensitive.
Serial configuration data input.
Serial configuration clock input.
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the f
OUT
output. OE = L low stops f
OUT
in the logic low stat
(f
OUT
= L, f
OUT
= H).
Negative power supply (GND).
Positive power supply for I/O and core. All V
CC
pins must be connected to the
positive power supply for correct operation.
PLL positive power supply (analog power supply).
Do not connect.
Function
S_LOAD
Input
0
LVCMOS
P_LOAD
Input
1
LVCMOS
S_DATA
S_CLOCK
M[0:6]
N[1:0]
OE
Input
Input
Input
Input
Input
0
0
1
1
1
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
GND
V
CC
V
CC_PLL
NC
Supply
Supply
Supply
Ground
V
CC
V
CC
Table 2. Output Frequency Range and PLL Post-Divider N
PWR_DOWN
0
0
0
0
1
1
1
1
N
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
VCO Output Frequency
Division
2
4
8
1
32
64
128
16
f
OUT
Frequency Range
200 – 450 MHz
100 – 225 MHz
50 – 112.5 MHz
400 – 900 MHz
12.5 – 28.125 MHz
6.25 – 14.0625 MHz
3.125 – 7.03125 MHz
25 – 56.25 MHz
MPC9239
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 3. Function Table
Input
XTAL_SEL
OE
PWR_DOWN
0
f
REF_EXT
Outputs disabled. f
OUT
is stopped in the logic low state
(f
OUT
= L, f
OUT
= H)
Output divider
÷
1
1
XTAL interface
Outputs enabled
Output divider
÷
16
Table 4. General Specifications
Symbol
V
TT
MM
HBM
LU
C
IN
θ
JA
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Input Capacitance
LQFP 32 Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
200
2000
200
4.0
83.1
73.3
68.9
63.8
57.4
59.0
54.4
52.5
50.4
47.8
23.0
86.0
75.4
70.9
65.3
59.6
60.6
55.7
53.8
51.5
48.8
26.3
Min
Typ
V
CC
– 2
Max
Unit
V
V
V
mA
pF
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Inputs
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
MIL-SPEC 883E
Method 1012.1
Condition
JESD 51-6, 2S2P multilayer test board
θ
JC
LQFP 32 Thermal Resistance Junction to Case
Table 5. Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
S
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
–65
Characteristics
Min
–0.3
–0.3
–0.3
Max
3.9
V
CC
+ 0.3
V
CC
+ 0.3
±20
±50
125
Unit
V
V
V
mA
mA
°C
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
MPC9239
4
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. DC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (f
REF_EXT
, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
V
IH
V
IL
I
IN
V
OH
V
OL
V
OH
V
OL
I
CC_PLL
I
CC
Input High Voltage
Input Low Voltage
Input Current
(1)
Output High Voltage
(3)
Output Low Voltage
(3)
Output High Voltage
(3)
Output Low Voltage
(3)
2.0
V
CC
+ 0.3
0.8
±200
V
V
µA
LVCMOS
LVCMOS
V
IN
= V
CC
or GND
LVPECL
LVPECL
Differential Clock Output f
OUT(2)
V
CC
–1.02
V
CC
–1.95
2.0
0.55
V
CC
–0.74
V
CC
–1.60
V
V
Test and Diagnosis Output TEST
V
V
I
OH
= –0.8 mA
I
OL
= 0.8 mA
V
CC_PLL
Pins
All V
CC
Pins
Supply Current
Maximum PLL Supply Current
Maximum Supply Current
62
20
100
mA
mA
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50
Ω
to V
TT
= V
CC
– 2 V.
3. The MPC9239 TEST output levels are compatible to the MC12429 output levels. The MPC9239 is capable of driving 25
Ω
loads.
Table 7. AC Characteristics
(V
CC
= 3.3 V ± 5%, T
A
= 0°C to +70°C)
(1)
Symbol
f
XTAL
f
VCO
f
MAX
Characteristics
Crystal Interface Frequency Range
VCO Frequency Range
(2)
Output Frequency
N = 11 (÷ 1)
N = 00 (÷ 2)
N = 01 (÷ 4)
N = 10 (÷ 8)
Min
10
800
400
300
100
50
0
50
45
0.05
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
S_DATA to S_CLOCK
M, N to P_LOAD
N = 11 (÷ 1)
N = 00 (÷ 2)
N = 01 (÷ 4)
N = 10 (÷ 8)
N = 11 (÷ 1)
N = 00 (÷ 2)
N = 01 (÷ 4)
N = 10 (÷ 8)
20
20
20
20
20
60
90
120
160
40
65
90
120
10
50
55
0.3
Typ
Max
20
1800
900
450
225
112.5
10
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ms
20% to 80%
PWR_DOWN = 0
Condition
f
S_CLOCK
t
P,MIN
DC
t
r
, t
f
t
S
Serial Interface Programming Clock Frequency
(3)
Minimum Pulse Width
Output Duty Cycle
Output Rise/Fall Time
Setup Time
(S_LOAD, P_LOAD)
t
S
t
JIT(CC)
Hold Time
Cycle-to-Cycle Jitter
t
JIT(PER)
Period Jitter
t
LOCK
Maximum PLL Lock Time
1. AC characteristics apply for parallel output termination of 50
Ω
to V
TT
.
2. The input frequency f
XTAL
and the PLL feedback divider M must match the VCO frequency range: f
VCO
= f
XTAL
⋅
2
⋅
M.
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. Refer to the application section for more details.
MPC9239
Advanced Clock Drivers Devices
Freescale Semiconductor
5
Microcontroller MCU
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