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P3C1024

Description
HIGH SPEED 128K x 8 3.3V STATIC CMOS RAM
File Size46KB,2 Pages
ManufacturerETC
Download Datasheet View All

P3C1024 Overview

HIGH SPEED 128K x 8 3.3V STATIC CMOS RAM

P3C1024
HIGH SPEED 128K x 8
3.3V STATIC CMOS RAM
FEATURES
3.3 Volts Power Supply
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 3.3 Volts
±
0.3 Volts Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
ADVANCE INFORMATION
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin DIP and SOJ
DESCRIPTION
The P3C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V
±
0.3V tolerance power
supply.
The P3C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
Access times of 20 nanoseconds permit greatly en- location is presented on the data input/output pins. The
hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either
reduce power consumption to a low level. The P3C1024
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
is a member of a family of PACE RAM™ products offer-
ing fast access times.
Package options for the P3C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
•••
PIN CONFIGURATION
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(9)
A
262,144-
BIT
MEMORY
ARRAY
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
1024.2
A16
A14
A12
A7
I/O
1
A6
INPUT
DATA
CONTROL
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
••• •••
••• •••
••• •••
COLUMN
I/O
I/O
2
COLUMN
SELECT
WE
CE1
CE2
OE
CONTROL
CIRCUIT
A
•••
•••
GND
A
1024.1
(8)
DIP , SOJ
TOP VIEW
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