GS82583EQ18/36GK-500/450/400
260-Pin BGA
Commercial Temp
Industrial Temp
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8Mb x 36 and 16Mb x 18 organizations available
500 MHz maximum operating frequency
1.0 BT/s peak transaction rate (in billions per second)
72 Gb/s peak data bandwidth (in x36 devices)
Separate I/O DDR Data Buses
Non-multiplexed DDR Address Bus
Two operations - Read and Write - per clock cycle
Burst of 2 Read and Write operations
3 cycle Read Latency
1.3V nominal core voltage
1.2V, 1.3V, or 1.5V HSTL I/O interface
Configurable ODT (on-die termination)
ZQ pin for programmable driver impedance
ZT pin for programmable ODT impedance
IEEE 1149.1 JTAG-compliant Boundary Scan
260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
288Mb SigmaQuad-IIIe™
Burst of 2 SRAM
Up to 500 MHz
1.3V V
DD
1.2V, 1.3V, or 1.5V V
DDQ
Clocking and Addressing Schemes
The GS82583EQ18/36GK SigmaQuad-IIIe SRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B2
SRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 SRAM is always one address pin
less than the advertised index depth (e.g. the 16M x 18 has 8M
addressable index).
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe SRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
SRAMs. Although very similar to GSI's second generation of
networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),
these third generation devices offer several new features that
help enable significantly higher performance.
Parameter Synopsis
Speed Grade
-500
-450
-400
Max Operating Frequency
500 MHz
450 MHz
400 MHz
Read Latency
3 cycles
3 cycles
3 cycles
V
DD
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
Rev: 1.07 12/2017
1/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583EQ18/36GK-500/450/400
16M x 18 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCH
(CFG)
MCL
(B4M)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
Q17
V
SS
Q16
V
SS
Q15
Q14
V
SS
CQ1
CQ1
V
SS
NU
O
NU
O
V
SS
NU
O
V
SS
NU
O
V
SS
V
DD
2
V
DDQ
NU
O
V
DDQ
NU
O
V
DDQ
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
V
SS
Q13
V
DDQ
Q12
Q11
V
DDQ
Q10
V
DDQ
Q9
V
DDQ
3
V
DD
V
SS
D17
V
SS
D16
V
SS
D15
D14
V
SS
V
REF
QVLD1
V
SS
NU
I
NU
I
V
SS
NU
I
V
SS
NU
I
V
SS
V
DD
4
V
DDQ
NU
I
V
DDQ
NU
I
V
DD
NU
I
NU
I
V
DDQ
NU
I
V
DD
V
ss
D13
V
DDQ
D12
D11
V
DD
D10
V
DDQ
D9
V
DDQ
9
PZT1
PZT0
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NC
(1152 Mb)
10
V
DDQ
D0
V
DDQ
D1
V
DD
D2
D3
V
DDQ
D4
V
DD
V
SS
NU
I
V
DDQ
NU
I
NU
I
V
DD
NU
I
V
DDQ
NU
I
V
DDQ
11
V
DD
V
SS
NU
I
V
SS
NU
I
V
SS
NU
I
NU
I
V
SS
V
REF
QVLD0
V
SS
D5
D6
V
SS
D7
V
SS
D8
V
SS
V
DD
12
V
DDQ
Q0
V
DDQ
Q1
V
DDQ
Q2
Q3
V
DDQ
Q4
V
DDQ
V
SS
NU
O
V
DDQ
NU
O
NU
O
V
DDQ
NU
O
V
DDQ
NU
O
V
DDQ
13
V
DD
V
SS
NU
O
V
SS
NU
O
V
SS
NU
O
NU
O
V
SS
CQ0
CQ0
V
SS
Q5
Q6
V
SS
Q7
V
SS
Q8
V
SS
V
DD
MCL
NC
(RSVD)
ZQ
MCH
(SIOM)
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NC
(576 Mb)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(x18)
V
DD
SA
V
SS
V
DDQ
MZT1
W
V
SS
CK
CK
V
SS
R
MZT0
V
DDQ
V
SS
NC
(RSVD)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(B2)
V
SS
TCK
TDO
V
DD
NC
(RSVD)
NC
(RSVD)
V
SS
TMS
TDI
MCL
ZT
MCL
MCL
Notes:
1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.07 12/2017
2/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583EQ18/36GK-500/450/400
8M x 36 Pinout (Top View)
5
6
7
8
NC
(RSVD)
MCL
(CFG)
MCL
(B4M)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
V
DD
V
SS
Q26
V
SS
Q25
V
SS
Q24
Q23
V
SS
CQ1
CQ1
V
SS
Q30
Q29
V
SS
Q28
V
SS
Q27
V
SS
V
DD
2
V
DDQ
Q35
V
DDQ
Q34
V
DDQ
Q33
Q32
V
DDQ
Q31
V
DDQ
V
SS
Q22
V
DDQ
Q21
Q20
V
DDQ
Q19
V
DDQ
Q18
V
DDQ
3
V
DD
V
SS
D26
V
SS
D25
V
SS
D24
D23
V
SS
V
REF
QVLD1
4
V
DDQ
D35
V
DDQ
D34
V
DD
D33
D32
V
DDQ
D31
V
DD
V
SS
D22
V
DDQ
D21
D20
V
DD
D19
V
DDQ
D18
V
DDQ
9
PZT1
PZT0
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD0
KD0
V
SS
MCH
V
SS
RST
V
SS
NC
(1152 Mb)
10
V
DDQ
D0
V
DDQ
D1
V
DD
D2
D3
V
DDQ
D4
V
DD
V
SS
D13
V
DDQ
D14
D15
V
DD
D16
V
DDQ
D17
V
DDQ
11
V
DD
V
SS
D9
V
SS
D10
V
SS
D11
D12
V
SS
V
REF
QVLD0
V
SS
D5
D6
V
SS
D7
V
SS
D8
V
SS
V
DD
12
V
DDQ
Q0
V
DDQ
Q1
V
DDQ
Q2
Q3
V
DDQ
Q4
V
DDQ
V
SS
Q13
V
DDQ
Q14
Q15
V
DDQ
Q16
V
DDQ
Q17
V
DDQ
13
V
DD
V
SS
Q9
V
SS
Q10
V
SS
Q11
Q12
V
SS
CQ0
CQ0
V
SS
Q5
Q6
V
SS
Q7
V
SS
Q8
V
SS
V
DD
MCL
NC
(RSVD)
ZQ
MCH
(SIOM)
MVQ
V
SS
SA
V
SS
SA
V
SS
SA
V
SS
KD1
KD1
V
SS
DLL
V
SS
MCH
V
SS
NC
(576 Mb)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
NU
I
(x18)
V
DD
SA
V
SS
V
DDQ
MZT1
W
V
SS
CK
CK
V
SS
R
MZT0
V
DDQ
V
SS
NC
(RSVD)
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
V
DD
V
DDQ
SA
V
DDQ
SA
V
DD
SA
V
DDQ
SA
(B2)
V
SS
D30
D29
V
SS
D28
V
SS
D27
V
SS
V
DD
V
SS
TCK
TDO
V
DD
NC
(RSVD)
NC
(RSVD)
V
SS
TMS
TDI
MCL
ZT
MCL
MCL
Notes:
1. Pins 6W, 7A, 8W, and 8Y must be tied Low in this device.
2. Pins 5R and 9N must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
5. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied Low in this device to select Burst-of-2 configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
7. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
8. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
9. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.07 12/2017
3/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583EQ18/36GK-500/450/400
Pin Description
Symbol
SA
D[35:0]
Description
Address
— Read Address is registered on
CK
and Write Address is registered on
CK.
Write Data
— Registered on
KD
and
KD
during Write operations.
D[17:0] - x18 and x36.
D[35:18] - x36 only.
Read Data
— Aligned with
CQ
and
CQ
during Read operations.
Q[17:0] - x18 and x36.
Q[35:18] - x36 only.
Read Data Valid
— Driven high one half cycle before valid Read Data.
Primary Input Clocks
— Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks
— Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD1, KD1: latch Write Data (D[35:18] in x36, D[17:9] in x18).
Read Data Output Clocks
— Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
Read Enable
— Registered on
CK.
R = 0 initiates a Read operation.
Write Enable
— Registered on
CK.
W = 0 initiates a Write operation.
DLL Enable
— Weakly pulled High internally.
DLL = 0: disables internal DLL.
DLL = 1: enables internal DLL.
Reset
— Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Driver Impedance Control Resistor Input
— Must be connected to V
SS
through an external resistor RQ to
program driver impedance.
ODT Impedance Control Resistor Input
— Must be connected to V
SS
through an external resistor RT to
program ODT impedance.
ODT Mode Select
— Set the ODT state globally for all input groups. Must be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
ODT Configuration Select
— Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Type
Input
Input
Q[35:0]
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
R
W
DLL
Output
Output
Input
Input
Output
Input
Input
Input
RST
ZQ
ZT
Input
Input
Input
MZT[1:0]
Input
PZT[1:0]
Input
Rev: 1.07 12/2017
4/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS82583EQ18/36GK-500/450/400
Symbol
MVQ
V
DD
V
DDQ
V
REF
V
SS
TCK
TMS
TDI
TDO
MCH
MCL
NC
Description
I/O Voltage Select
— Indicates what voltage is supplied to the V
DDQ
pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V or 1.3V nominal V
DDQ
.
MVQ = 1: Configure for 1.5V nominal V
DDQ
.
Core Power Supply
I/O Power Supply
Input Reference Voltage
— Input buffer reference voltage.
Ground
JTAG Clock
— Weakly pulled Low internally.
JTAG Mode Select
— Weakly pulled High internally.
JTAG Data Input
— Weakly pulled High internally.
JTAG Data Output
Must Connect High
— May be tied to V
DDQ
directly or via a 1k resistor.
Must Connect Low
— May be tied to V
SS
directly or via a 1k resistor.
No Connect
— There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input
— There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Output
— There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
Type
Input
—
—
—
—
Input
Input
Input
Output
Input
Input
—
NU
I
NU
O
Input
Output
Rev: 1.07 12/2017
5/26
© 2014, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
京公网安备 11010802033920号
EEWORLD
