When either shunt switch is on, the Rp2 on that side reduces to
this value
Normal operation with shunt switches open
Rp2
2
Quality Factor (RF2 Port Grounded,
Inductance Removed) (Q)
State 0
State 31
State 63
State 0
State 31
23
17
15
42
f = 2GHz
8
f = 1GHz
Series Configuration, Nonlinear
Parameters
Second Harmonic, 2-f
0
(P
2H SERIES
)
States 0 to 3
States 4 to 63
States 0 to 63
Third Harmonic, 3-f
0
(P
3H SERIES
)
States 0 to 7
States 8 to 63
-60
-59
-34
-40
dBm
dBm
P
FWD
= 35dBm, f
0
= 900MHz
P
FWD
= 36dBm, f
0
= 900MHz
-72
-55
-70
-43
-40
dBm
dBm
dBm
P
FWD
= 35dBm, f
0
= 900MHz
P
FWD
= 36dBm, f
0
= 900MHz
P
FWD
= 33dBm, f
0
= 1910MHz
RF Micro Devices Inc. 7628 Thorndike Road, Greensboro, NC 27409-9421
For sales or technical support, contact RFMD at +1.336.678.5570 or
customerservice@rfmd.com.
DS140530
The information in this publication is believed to be accurate. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents or other rights of
third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended
application circuitry and specifications at any time without prior notice.
3 of 15
RFAC3612
Specification
Parameter
Min
States 0 to 63
Unit
Typ
-65
Condition
P
FWD
= 33dBm, f
0
= 1910MHz
Max
dBm
Series Configuration, Nonlinear
Parameters – Cont.
Input IP2 – States 0 to 63 (IP2
SERIES
)
Cell Low
Cell High
IMT Low
IMT High
GPS Test 1
GPS Test 2
Band 8 (800MHz to 960MHz)
Bands 2, 4, 7, 11 (1428MHz to 2690MHz)
Input IP3 (States 0 to 63 (IP3
SERIES
)
Cell (B5)
IMT (B1)
SV – LTE Test 1
SV – LTE Test 2
Band 8 (800MHz to 960MHz)
Bands 2, 4, 7, 11 (1428MHz to 2690MHz)
RF1 to RF2 Spurious (all States
No RF
915MHz at 35dBm
1910MHz at 33dBm
-120
-112
-113
dBm
dBm
dBm
400MHz to 2700MHz
925MHz to 960MHz
1930MHz to 1990MHz
75
76
77
85
76
70
dBm
dBm
See IP2 / IP3 test conditions table below
dBm
dBm
dBm
dBm
Tone 1 at 20dBm
Tone 2 at -15dBm
115
132
129
130
140
140
126
128
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Tone 1 at 20dBm
Tone 2 at -15dBm
See IP2 / IP3 test conditions table below
See IP2 / IP3 test conditions table below
General Electrical Specifications
Power-up Time (t
POWER-UP
)
Switching Time-Small Signal (t
SWITCH, SS
)
Stitching Time – Large Signal (t
SWITCH, LS
)
75
15
75
µs
µs
µs
Time from VDD within specification to all specifications is met.
Time from programming (falling edge of SCLK of the 16
th
bit) to
90% of capacitance change achieved
Time from programming (falling edge of SCLK of the 16
th
bit) to
power handling and linearity specifications are met
3-Wire Interface Timing
Characteristics
Serial Clock Frequency (f
SCLK
= 1/t
SCLK
)
Clock High and Low Time (t
SCLKHIGH
,
t
SCLKLOW
)
Falling Edge of CS to Rising Edge of SCLK
Set-up Time, Start of Telegram (t
CS_SCLK
)
3
26
0.45 x
t
SCLK
10
0.55 x
t
SCLK
MHz
ns
RF Micro Devices Inc. 7628 Thorndike Road, Greensboro, NC 27409-9421
For sales or technical support, contact RFMD at +1.336.678.5570 or
customerservice@rfmd.com.
DS140530
The information in this publication is believed to be accurate. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents or other rights of
third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended
application circuitry and specifications at any time without prior notice.
4 of 15
RFAC3612
Specification
Parameter
Min
Falling Edge of SCLK to Rising Edge of CS
Set-up Time, End of Telegram (t
SCLK_SC
)
20
Unit
Typ
Max
ns
Condition
3-Wire Interface Timing
Characteristics – Cont.
SDATA to Falling Edge of SCLK Set-up Time
(t
SDATA_SCLK
)
SDATA Hold Time After Falling Edge of
SCLK (t
SDATA
)
CS High Time for Activation of Programmed
Bits (t
CSHIGH
)
10
10
100
ns
ns
ns
NOTES:
1. RF1 and RF2 ports are internally DC coupled and should not have any non-zero DC bias voltage during operation.
2. Equivalent circuit below for C
S
, Cp, R
S,
L
S/2,
Rp1, and Rp2
3. Corresponds to a minimum clock cycle time of 38.5ns.
RF Micro Devices Inc. 7628 Thorndike Road, Greensboro, NC 27409-9421
For sales or technical support, contact RFMD at +1.336.678.5570 or
customerservice@rfmd.com.
DS140530
The information in this publication is believed to be accurate. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents or other rights of
third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended
application circuitry and specifications at any time without prior notice.
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