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PLL650-07SC

Description
LOW COST Network LAN Clock SOURCE
File Size205KB,4 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Compare View All

PLL650-07SC Overview

LOW COST Network LAN Clock SOURCE

PLL650-07
LOW COST Network LAN Clock SOURCE
FEATURES
PIN CONFIGURATION
XOUT
GNDA
VDD50M
50MHz
GND50M
50MHz
VDD25M
1
2
14
13
XIN
VDDA
NC
GND
25MHz
GND25M
25MHz
Full CMOS output swing with 40-mA output drive
capability. 25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
2 outputs fixed at 50MHz, 2 outputs fixed at 25MHz .
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.3V operation.
Available in 14-Pin 150mil SOIC
.
PLL 650-07
3
4
5
6
7
12
11
10
9
8
DESCRIPTION
The PLL650-07 is a low cost, low jitter, high
performance clock synthesizer. With PhaseLink’s
proprietary analog Phase Locked Loop techniques, this
device can produce multiple clock outputs from a 25.0MHz
crystal or reference clock. This makes the PLL650-07 an
excellent choice for systems requiring clocking for network
chips and ASICs.
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
Phase
Detector
Charge
Pump
+
Loop
Filter
VCO
Post
Divider
2
50MHz
VCO
Divider
2
25MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1

PLL650-07SC Related Products

PLL650-07SC PLL650-07 PLL650-07SI PLL650-07SC-R P650-07SC
Description LOW COST Network LAN Clock SOURCE LOW COST Network LAN Clock SOURCE LOW COST Network LAN Clock SOURCE LOW COST Network LAN Clock SOURCE LOW COST Network LAN Clock SOURCE
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