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P500-X7BDC

Description
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
File Size193KB,5 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet View All

P500-X7BDC Overview

Low Power CMOS Output VCXO Family (17MHz to 130MHz)

PLL500-17B/27B/37B
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
FEATURES
VCXO output for the 17MHz to 130MHz range
-
PLL500-17B: 17MHz to 36MHz
-
PLL500-27B: 27MHz to 65MHz
-
PLL500-37B: 65MHz to 130MHz
Low phase noise (-142 dBc @ 10kHz offset).
CMOS output with OE tri-state control.
Selectable output drive (Standard or High drive).
-
Standard: 8mA drive capability at TTL level.
-
High: 24mA drive capability at TTL level.
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5 to 3.3V operation.
Available in 8-Pin SOIC or DIE.
PIN CONFIGURATION
XIN
OE^
VIN
GND
1
8
XOUT
DS^
VDD*
CLK
P500-x7B
2
3
4
7
6
5
^: Denotes internal Pull-up
DIE PAD LAYOUT
32 mil
(812,986)
8
1
XIN
XOUT
DRIVSEL^ 7
39 mil
DESCRIPTION
The PLL500-17B/27B/37B are a low cost, high per-
formance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc at 10kHz offset. The very low jitter (2.5
ps RMS period jitter) makes these chips ideal for
applications requiring voltage controlled frequency
sources. The IC’s are designed to accept fundamen-
tal resonant mode crystals.
2
OE^
VDD 6
3 VCON
4 GND
CLK 5
DIE ID:
PLL500-17B: C500A0505-05P
Y
X
PLL500-27B: C500A0505-05Q
PLL500-37B: C500A0505-05R
(0,0)
Note: ^ denotes internal pull up
FREQUENCY RANGE
PART #
PLL500-17B
PLL500-27B
PLL500-37B
MULTIPLIER
No PLL
No PLL
No PLL
FREQUENCY
17 – 36 MHz
27 – 65 MHz
65 – 130 MHz
DIE SPECIFICATIONS
Name
Value
Size
Reverse side
Pad dimensions
Thickness
39 x 32 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 12/21/05 Page 1
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