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P520-00DC

Description
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
File Size214KB,8 Pages
ManufacturerPLL (PhaseLink Corporation)
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P520-00DC Overview

Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)

PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FEATURES
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz – 1GHz (LVDS output
only for 8x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DIE CONFIGURATION
65 mil
OUTSEL0^
OUTSEL1^
SEL0^
SEL1^
VDD
VDD
VDD
VDD
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
XIN
XOUT
SEL3^
62 mil
26
27
Die ID:
A1919-19A
15
28
14
13
SEL2^
OE
CTRL
VCON
29
12
11
30
DESCRIPTION
PLL520-00 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
C502A
31
1
2
3
4
5
6
7
8
10
9
Y
(0,0)
X
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OE_SELECT
(Pad #9)
0
OUTSEL0
(Pad #25)
0
1
0
1
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Tri-state
Output enabled
Output enabled
Tri-state
BLOCK DIAGRAM
SEL
OE
VCON
Oscillator
Amplifier
w/
XIN
integrated
varicaps
PLL
(Phase
Locked
Loop)
Q
Q
XOUT
PLL by-pass
PLL520-00
1 (Default)
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
65 x 62 mil
GND
80 micron x 80 micron
10 mil
Pad #9, 18, 25: Bond to GND to set to “0”. No connection results to
“default” setting through internal pull-up.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “1”
Logical states defined by CMOS levels if OE_SELECT is “0
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
GNDBUF
GND
GND
GND
GND
GND
NC
GND

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