552AH000122DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> 552AH000122DG

552AH000122DG: DescriptionVCXO Oscillators VCXO; Diff/SE; Dual Freq; 10-1417 MHz; CategoryPassive components; File Size341KB，15 Pages; ManufacturerSilicon Laboratories

Download Datasheet Parametric View All

552AH000122DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	552AH000122DG	-	-	View	Buy Now

552AH000122DG Overview

VCXO Oscillators VCXO; Diff/SE; Dual Freq; 10-1417 MHz

552AH000122DG Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	Silicon Laboratories
Product Category	VCXO Oscillators
Frequency	10 MHz to 945 MHz
Frequency Stability	20 PPM
Load Capacitance	15 pF
Operating Supply Voltage	3.3 V
Supply Voltage - Min	2.97 V
Supply Voltage - Max	3.63 V
Output Format	LVPECL
Termination Style	SMD/SMT
Package / Case	5 mm x 7 mm
Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C
Length	7 mm
Height	1.65 mm
Width	5 mm
Packaging	Tray
Current Rating	120 mA
Duty Cycle - Max	55 %
Mounting Style	SMD/SMT

Preview

Download Datasheet

View All

Si 5 5 2

EVISION

U A L

REQUENCY

OLTAGE

- C

ON TROLLED

R Y S TA L

SCILLATOR

( V C X O ) 1 0 MH

Z TO

1.4 G H

Features



Available with any-rate output

frequencies from 10–945 MHz and

selected frequencies to 1.4 GHz



Two selectable output frequencies



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than

SAW-based oscillators



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Applications



Ordering Information:



SONET/SDH



xDSL



10 GbE LAN/WAN

Low-jitter clock generation



Optical modules



Clock and data recovery

See page 10.

Description

The Si552 dual-frequency VCXO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a very low jitter clock for all output frequencies.

The Si552 is available with any-rate output frequency from 10 to 945 MHz

and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a

different crystal is required for each output frequency, the Si552 uses one

fixed crystal frequency to provide a wide range of output frequencies. This

IC-based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides superior supply noise rejection, simplifying the task of generating

low-jitter clocks in noisy environments typically found in communication

systems. The Si552 IC-based VCXO is factory-configurable for a wide

variety of user specifications including frequency, supply voltage, output

format, tuning slope, and temperature stability. Specific configurations are

factory programmed at time of shipment, thereby eliminating the long lead

times associated with custom oscillators.

Pin Assignments:

See page 9.

(Top View)

CLK–

GND

CLK+

Functional Block Diagram

CLK- CLK+

Fixed

Frequency XO

Any-rate

10–1400 MHz

DSPLL

Clock Synthesis

ADC

GND

Rev. 1.1 4/13

Si552

Recommended Resources

Switch signal generation circuit

Field effect transistor op amp circuit diagram

Center offset calculation circuit

XY servo mechanism control circuit diagram

555 long delay circuit (1)

Voice control delay power saving switch

CE5.0 debug version NK compilation error!: I have never used the DEBUG version of NK. Today, after compiling, an error occurred: kitl.lib(ethdbg.obj) : error LNK2001: unresolved external symbol dpCurSettings. This error occurred when compiling...; dm29769671 Embedded System

2009 The saddest year: iSuppli, a market research organization, released a preliminary statistical report on the top 20 semiconductor manufacturers in the world in 2009. Although the entire industry is gloomy, only one of t...; 西点 FPGA/CPLD

Questions about the 2x in-phase proportional operational amplifier composed of OPA380: As shown in the figure, there are two questions: 1. Why is the amplitude-frequency gain in the Bode plot not 6dB, but slightly greater than 6dB (6.02dB, as shown in the blue box in the figure)? Is it ...; xiaxingxing Analog electronics

Increase performance in imaging applications by integrating DSP functions in FPGAs: This article describes the development of an embedded system for a small, high-performance, ultra-low-cost camera. Initially, a digital signal processor, several ASSPs, and external memory were used. ...; lorant FPGA/CPLD

Upload an ST-LINK firmware update software: I found it online. My ST-LINK was very old. The new version of MDK said that my firmware was old. I found this on the Internet. It is now old. I can use ST-LINK under MDK4.6. I dare not keep it to mys...; ddllxxrr stm32/stm8

Helper2416-18——Ninth Bare Metal Part——MMU & Exception Handling Practice + Practice Source Code: [i=s]This post was last edited by yuanlai2010 on 2014-7-23 20:52[/i] [align=center][b][font=楷体, 楷体_GB2312][size=5][color=#0000ff]Nine Parts of Bare Metal - MMU & Exception Handling Practice[/color][/s...; yuanlai2010 Embedded System

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components