Preliminary
PLL502-10
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
FEATURES
•
•
•
•
•
•
•
•
•
750kHz to 400MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz).
Selectable CMOS, PECL and LVDS output.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (+/-190 ppm)
3.3V operation.
Available in DIE (65 mil x 62 mil).
Y
DIE CONFIGURATION
65 mil
(1550,1475)
19
18
17
16
25
26
24
23
22
21
20
27
15
28
14
62 mil
13
29
12
11
30
10
31
1
2
3
4
5
6
7
8
9
(0,0)
DESCRIPTIONS
The PLL502-10 is a monolithic low jitter and low
phase noise (-140dBc/Hz @ 10kHz offset) VCXO IC
Die, with CMOS, LVDS and PECL output, covering
the 750kHz to 400MHz output range. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from F
XIN
/ 16 to F
XIN
x 16
thanks to frequency selector pads. This makes the
PLL502-10 ideal as a universal die for applications
ranging from ADSL to SONET.
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
OE_SELECT
(Pad #9)
0
1 (Default)
Pad #25
OUTSEL0
0
1
0
1
OE_CTRL
(Pad #30)
0 (Default)
1
0
1 (Default)
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
State
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
VCO
Divider
Charge
Pump
SEL
Reference
Divider
Phase
Detector
+
Loop
Filter
VCO
CLKBAR
CLK
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 1
Preliminary
PLL502-10
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
FREQUENCY SELECTION TABLE
Pad #28
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
Pad #29
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Pad #19
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Pad #20
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Selected Multiplier
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Fin / 8
Fin x 2
Reserved
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
1
1
1
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 2
Preliminary
PLL502-10
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
V
SS
-0.5
V
SS
-0.5
-65
-40
MAX.
7
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
at VCON = 1.65V
AT cut
AT cut
MIN.
12
TYP.
MAX.
25
UNITS
MHz
pF
9.5
250
30
-
Ω
Note:
Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at
nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This
however may reduce the pull range.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
0V
≤
VCON
≤
3.3V, -3dB
2000
25
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 - 25MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
MIN.
380
±190
TYP.
10
MAX.
UNITS
ms
ppm
ppm
5
115
10
%
ppm/V
kΩ
kHz
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 3
Preliminary
PLL502-10
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock Duty
Cycle
Short Circuit Current
SYMBOL
I
DD
CONDITIONS
Fout < 24MHz
PECL/LVDS/CMOS
24MHz < Fout < 96MHz
96MHz < Fout < 400MHz
MIN.
TYP.
MAX.
25/25/15
65/45/30
100/80/40
UNITS
mA
V
DD
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
3.13
45
45
45
50
50
50
±50
3.47
55
55
55
V
%
mA
5. Jitter specifications
PARAMETERS
Period jitter RMS
CONDITIONS
With capacitive decoupling between
VDD and GND.
With capacitive decoupling between
VDD and GND. Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
MIN.
TYP.
5
8
9
TBM
3
MAX.
UNITS
ps
Accumulated jitter RMS
Integrated jitter RMS
155.52MHz
155.52MHz
ps
4
ps
6. Phase noise specifications
PARAMETERS
Phase Noise relative to
carrier
FREQUENCY
19.44MHz
106.25MHz
155.52MHz
@10Hz
-60
-60
-60
@100Hz
-90
-90
-90
@1kHz
-112
-112
-112
@10kHz
-140
-127
-125
@100kHz
-150
-125
-123
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 4
Preliminary
PLL502-10
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
7. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
8. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
1.1
1.2
3
±1
-5.7
V
out
= V
DD
or GND
V
DD
= 0V
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 5
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