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PLL502-10DI

Description
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
File Size128KB,8 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Compare View All

PLL502-10DI Overview

750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)

Preliminary
PLL502-10
750kHz – 400MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
FEATURES
750kHz to 400MHz output range.
Low phase noise output (@ 10kHz frequency
offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for
106.25MHz, -125dBc/Hz for 155.52MHz).
Selectable CMOS, PECL and LVDS output.
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Output Enable selector.
Wide pull range (+/-190 ppm)
3.3V operation.
Available in DIE (65 mil x 62 mil).
Y
DIE CONFIGURATION
65 mil
(1550,1475)
19
18
17
16
25
26
24
23
22
21
20
27
15
28
14
62 mil
13
29
12
11
30
10
31
1
2
3
4
5
6
7
8
9
(0,0)
DESCRIPTIONS
The PLL502-10 is a monolithic low jitter and low
phase noise (-140dBc/Hz @ 10kHz offset) VCXO IC
Die, with CMOS, LVDS and PECL output, covering
the 750kHz to 400MHz output range. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from F
XIN
/ 16 to F
XIN
x 16
thanks to frequency selector pads. This makes the
PLL502-10 ideal as a universal die for applications
ranging from ADSL to SONET.
X
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
OE_SELECT
(Pad #9)
0
1 (Default)
Pad #25
OUTSEL0
0
1
0
1
OE_CTRL
(Pad #30)
0 (Default)
1
0
1 (Default)
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
State
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
VCO
Divider
Charge
Pump
SEL
Reference
Divider
Phase
Detector
+
Loop
Filter
VCO
CLKBAR
CLK
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 1

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Description 750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals) 750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals) 750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals) 750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
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