Preliminary
PLL502-22
384MHz – 768MHz Low Phase Noise LVDS VCXO (12 – 24MHz Crystal)
FEATURES
•
•
•
•
•
•
•
•
Low phase noise output for the 384MHz to
768MHz range (-130 dBc at 10kHz offset).
LVDS output.
12 to 24MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
Wide pull range (+/-180 ppm)
3.3V operation.
Available in 16 Pin TSSOP or SOIC.
PIN CONFIGURATION
VDD
VDD
XIN
XOUT
OE
VIN
GND
1
2
16
15
VDD
GND_BUF
CLKBAR
VDD_BUF
CLK
GND_BUF
GND
GND
PLL 502-22
3
4
5
6
7
8
14
13
12
11
10
9
DESCRIPTION
The PLL502-22 is a monolithic low jitter and low
phase noise (-130dBc/Hz @ 10kHz offset) VCXO IC
with LVDS output, for 384MHz to 768MHz output
range. It allows the control of the output frequency
with an input voltage (VIN), using a low cost crystal.
The chip provides a pullable output at a frequency of
F
XIN
x 32. This makes the PLL502-22 ideal for a wide
range of applications, including 622.08MHz for
SONET.
GND
F
OUT
= F
XIN
x 32
OE (Pin 5)
0
1 (Default)
Output State
Tri-state
Output enabled
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLKBAR
CLK
XIN
XOUT
XTAL
OSC
VARICAP
OE
VIN
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 1
Preliminary
PLL502-22
384MHz – 768MHz Low Phase Noise LVDS VCXO (12 – 24MHz Crystal)
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
OE
VIN
GND
GND_BUF
CLK
VDD_BUF
CLKB
Number
1,2,16
3
4
5
6
7,8,9,10
11,15
12
13
14
Type
P
I
I
I
I
P
P
O
P
O
Crystal input pin.
Crystal output pin.
Output enable input pin. Disables (tri-state) output when low. Internal
pull-up enables output by default if pin is not connected to low.
Frequency control voltage input pin.
GND Power connectors.
GND connector for output buffers.
True clock output pin.
+3.3V Power supply connector for output buffers.
Complementary clock output pin.
Description
+3.3V Power supply connectors.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
V
SS
-
0.5
V
SS
-
0.5
-65
0
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
150
70
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 2
Preliminary
PLL502-22
384MHz – 768MHz Low Phase Noise LVDS VCXO (12 – 24MHz Crystal)
2. Crystal Specifications
PARAMETERS
Crystal Resonator
Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L
(xtal)
C
0
/C
1 (xtal)
R
E
AT cut
CONDITIONS
Parallel Fundamental
Mode
MIN.
12
TYP.
MAX.
24
UNITS
MHz
pF
TBD
250
30
AT cut
-
Ω
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
Output Frequency Synthesis
Error
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
(Unless otherwise noted in
Frequency Table)
MIN.
TYP.
10
MAX.
UNITS
ms
±30
ppm
VCXO Tuning Range
CLK output pullability
Linearity
VCXO Tuning Characteristic
F
XIN
= 12 - 24MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
380
±190
5
115
10
ppm
ppm
%
ppm/V
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
Supply Current, Dynamic
(with Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
@ 1.25V (LVDS)
LVDS
3.13
45
50
±50
CONDITIONS
MIN.
TYP.
MAX.
60
3.47
55
UNITS
mA
V
%
mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 3
Preliminary
PLL502-22
384MHz – 768MHz Low Phase Noise LVDS VCXO (12 – 24MHz Crystal)
5. Jitter and Phase Noise specification
PARAMETERS
Period jitter RMS
Accumulated jitter RMS
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
622MHz @100Hz offset
622MHz @1kHz offset
622MHz @10kHz offset
622MHz @100kHz offset
MIN.
TYP.
7
11
-80
-109
-130
-132
MAX.
UNITS
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
6. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
V
out
= V
DD
or GND
V
DD
= 0V
R
L
= 100
Ω
(see figure)
CONDITIONS
MIN.
247
-50
1.4
0.9
1.125
0
1.1
1.2
3
±1
-5.7
1.375
25
±10
-8
TYP.
355
MAX.
454
50
1.6
UNITS
mV
mV
V
V
V
mV
uA
mA
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 4
Preliminary
PLL502-22
384MHz – 768MHz Low Phase Noise LVDS VCXO (12 – 24MHz Crystal)
7. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 07/17/01 Page 5
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