PLL702-01 datasheet, PDF - EEWORLD Datasheet

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PLL702-01: DescriptionClock Generator for PowerPC Based Applications; File Size267KB，8 Pages; ManufacturerPLL (PhaseLink Corporation)

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PLL702-01 Overview

Clock Generator for PowerPC Based Applications

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PLL702-01

Clock Generator for PowerPC Based Applications

FEATURES

•

PIN ASSIGNMENT (28 pin SSOP)

CPUDRV_SEL^

XIN

XOUT / ASIC2_OE*^

VDD_ANA

VDD_DIG

VDD_PC I

PCI / PCI_SEL*

GND_PCI

GND_USB

VDD_USB

USB / USB_SEL*

VDD_ASIC2

ASIC2 A

ASIC2 B

Note :

1 CPU Clock output with selectable frequencies (50,

66, 75, 80, 83, 90, 100,125 or 133 MHz).

1 ASIC output clock (at CPU clock or CPU clock ÷ 2).

2 ASIC output clocks (at CPU clock) w/ output enable.

1 PCI output clock w/ output enable

1 Selectable 48, 30 or 12MHz (USB) output.

Selectable Spread Spectrum (SST) for EMI reduction

on ASIC and CPU.

PowerPC compatible output and drive CPU Clock.

Selectable reduced 67% drive strength on CPU Clock

Advanced, low power, sub-micron CMOS processes.

14.31818MHz fundamental crystal input.

3.3V and/or 2.5V operation.

Available in 28-Pin 209mil SSOP (QSOP)

CLK_SEL0

CLK_SEL1

SSCO

SSC1

GND_ANA

GND_CPU

CP U

VDD_CPU

VDD_ASIC1

ASIC1

GND_ASIC1

ASIC1_SEL

GND_DIG

GND_ASIC2

^: Internal pull-up resistor

Selectable reduced drive

strength

DESCRIPTION

The PLL702-01 is a low cost, low jitter, and high

performance clock synthesizer for generic PowerPC based

applications. It provides one CPU clock, three ASIC

outputs, one PCI output, and a selectable 48, 30 or 12MHz

(USB) output. The user can choose between 9 different

CPU clock frequencies, while the ASIC output can be

identical or half of the CPU frequency. Low EMI Spread

Spectrum Technology is available for the CPU, ASIC and

PCI clocks. The CPU drive strength is user selectable from

100% to 67%. All frequencies are generated from a single

low cost 14.31818MHz crystal. The CPU and ASIC clock

can be driven from an independent 2.5V power supply.

FREQUENCY TABLES

CLK_SEL1

CLK_SEL0

CPU

(MHz)

ASIC1 (MHz)

ASIC1_SEL

PLL702-01

*: Bi-directional pin

Tri-level input

ASIC2

(MHz)

PCI* (MHz)

PCI_SEL

Notes:

100

125

133

100

125

133

37.5

41.5

62.5

66.5

100

125

133

62.5

66.7

62.5

66.7

62.5

65.5

31.25

33.35

31.25

33.35

31.25

32.75

When CPU=90MHz, it implements 88.88MHz to meet PCI=33.3MHz/66.6MHz; When

CPU=133MHz, it implements 130.9MHz to meet Power PC clock AC Timing Specification.

* PCI_SEL=1 sets the Tri-state (output disabled) mode of the output.

BLOCK DIAGRAM

USB_SEL

Control

Logic

PLL

USB

CPU_CLK

PLL

SST

DIV 2

ASIC2_OE

PCI

PCI_OE

Control

Logic

ASIC1

ASIC2(A:B)

XIN

XOUT

SSC(0:1)

CLK_SEL(0:1)

ASIC1_SEL

PCI_SEL

XTAL

OSC

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 07/18/05 Page 1

PLL702-01

Clock Generator for PowerPC Based Applications

USB OUTPUT FREQUENCY AND CPU DRIVE STRENGTH SELECTION TABLES

USB_SEL

USB

48 MHz

30 MHz

12 MHz

CPUDRV_SEL

CPU drive strength

67% (reduced)

100% (nominal)

SPREAD SPECTRUM SELECTION TABLE

SSC1

SSC0

Spread Spectrum Modulation

OFF

- 0.50% – Downspread

- 1.00% – Downspread

- 1.25% – Downspread

FUNCTIONAL DESCRIPTION

Tri-level and two-level inputs

In order to reduce pin usage, the PLL702-01 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =

Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are

in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to

GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.

Connecting a bi-directional pin

The PLL702-01 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs

have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can

be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in

order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-

up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin

and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-

directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up

resistor.

Note:

when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up

resistor may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.

For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the

internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the

pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is

recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application

Diagram).

Note:

when the output is used to drive a load presenting an small resistance between the output pin and VDD, this

resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may

have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is

particularly true when driving 74FXX TTL components.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 07/18/05 Page 3

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