Preliminary
PLL702-03
Low EMI Peripheral Clock Generator for Notebook PCs
FEATURES
•
•
•
•
•
•
•
•
•
PIN ASSIGNMENT
Single Low EMI IC to replace multiple crystals and
oscillators on Notebooks and Motherboards (27MHz,
8MHz, 12MHz, 24.576MHz, 25MHz).
Single crystal input: 24.576MHz (accuracy requirement
+/- 20ppm)
Less than 10ppm Frequency Synthesis error, meeting
AC97, IEEE1394, IEEE802 and USB2.0 frequency
precision specification.
27MHz clock with 5 levels of Selectable Spread
Spectrum modulation form +/- 0.5% to +/- 1.5% center.
25MHz clock with double drive strength (Ethernet PHY
and MAC).
24.576MHz clocks for Audio Codec and IEEE1394.
Selectable 12MHz (USB 2.0) or 8MHz (Keyboard
controller).
Dual power source selection for 24.576MHz, 8MHz, and
12MHz.
Available in 16-Pin SOIC or TSSOP.
VDDOSC
XIN
XOUT
VSSOSC
VSSB1
24.576MHz/SST0*
T
24.576MHz/SST1*
v
VDDB1
1
2
16
15
VDDB2
27MHz
VSSB2
8MHz
12MHz/VDD_SEL*
v
VSS25M
25MHzx2
VDD25M
PLL 702-03
3
4
5
6
7
8
14
13
12
11
10
9
Note:
25MHzx2: double drive strength
*: Bi-directional pin
v
: Internal pull-down resistor (120k
Ω)
T
: Tri-level input
Table 1. SPREAD SPECTRUM SELECTION
SST1
1
1
1
0
0
0
SST0
1
0
M
1
0
M
SST Modulation only on
27MHz. (pin 15)
+/- 1.5 %
+/- 1.25 %
+/- 1 %
+/- 0.75 %
+/- 0.5 %
SST OFF (Default)
POWER GROUPS
•
•
•
VDDOSC –
VSSOSC: XIN, XOUT, analog core and
digital part.
VDDB1 –
VSSB1: 24.576MHz.
VDDB2 –
VSSB2: 27MHz, 8MHz, and 12MHz.
VDD25M –
VSS25M: 25MHz, (also used for 12MHz,
8MHz when power VDDB2 is not present, and
24.576MHz when power VDDB1 is not present).
•
Notes: M = Do not connect. 1 = Pulled up. 0 = Pulled down.
Table 2. POWER SELECTION TABLE
VDD_SEL
0
1
24.576MHz
(pin 7)
VDDB1
VDD25M
12MHz (pin 12)
8MHz (pin 13)
VDDB2
VDD25M
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/06/02 Page 1
Preliminary
PLL702-03
Low EMI Peripheral Clock Generator for Notebook PCs
BLOCK DIAGRAM
VDDB2
SSC(0:1)
XIN
XOUT
XTAL
OSC
PLL
SST
27_14.318MHz
VDD25M
VDDB1
VDDB1
24.576MHz
(pin7)
24.576MHz
(pin6)
25MHz
VDD25M
VDD25M
VDDB2
PLL2
VDD25M
VDDB2
12MHz
8MHz
Note:
In order to use VDD25M as power source for 8MHz (pin 13), 24.576MHz (pin 7), and 12MHz (pin 12), it is necessary to select this feature
through the VDD_SEL input (see Power Selection Table on p.1).
Note 2:
Only 27MHz output is modulated for low EMI via Spread Spectrum.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/06/02 Page 2
Preliminary
PLL702-03
Low EMI Peripheral Clock Generator for Notebook PCs
PIN DESCRIPTIONS
Name
VDDOSC
XIN
XOUT
VSSOSC
VSSB1
24.576MHz/SST0
Pin#
1
2
3
4
5
6
Type
P
I
O
P
P
B
Description
3.3V power supply for oscillator, analog core and digital circuitry.
Crystal input: for 24.576MHz fundamental crystal (CL = 20pF, parallel resonant mode, +/-
20ppm). On-chip load capacitors: no external load capacitors required.
Crystal output.
Ground connection.
Ground connection.
Bi-directional and Tri-Level pin. Upon power-on, the value of SST0 is latched in and used
to select the SST control (see Spread Spectrum selection table 1). Tri level input: M = Do
not connect, 1 = Pull up, 0 = Pull down. After power-up this pin acts as 24.576MHz output
clock.
Bi-directional pin. Upon power-on, the value of SST1 is latched in and used to select the
SST control (see Spread Spectrum selection table 1). Internal pull down defaults SST1 to
0, use external pull-up to set to 1. After power-up this pin acts as 24.576MHz output clock.
3.3V power supply for 24.576MHz clock.
3.3V power supply for 25MHz, 8MHz, 12MHz, 24.576MHz.
25MHz Ethernet output clock (double drive strength).
Ground connection.
Bi-directional pin. Upon power-on, the value of VDD_SEL is latched in and used to select
the power (see Power Selection table 2 ). Internal pull down defaults SST1 to 0, use
external pull-up to set to 1. After power-up this pin acts as 12MHz output clock.
8MHz output clock (for Keyboard controller).
Ground connection.
27MHz output. This output can be modulated for low EMI using SST (Spread Spectrum
Technology).
3.3V power supply for 27MHz, 20MHz, 12MHz, and 24.576MHz.
24.576MHz/SST1
VDDB1
VDD25M
25MHzx2
VSS25M
12MHz/VDD_SEL
8MHz
VSSB2
27MHz
VDDB2
7
8
9
10
11
12
13
14
15
16
B
P
P
O
P
B
O
P
O
P
FUNCTIONAL DESCRIPTION
Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-02 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =
Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are
in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to
GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/06/02 Page 3
Preliminary
PLL702-03
Low EMI Peripheral Clock Generator for Notebook PCs
Connecting a bi-directional pin
The PLL702-03 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs
have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can
be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in
order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-
up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin
and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-
directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up
resistor.
Note:
when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor
may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.
For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the
internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is
recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application
Diagram).
Note:
when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is
in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be
dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is particularly
true when driving 74FXX TTL components.
APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Internal to chip
VDD
External Circuitry
R
up
Power Up
Reset
R
RB
Output
EN
Bi-directional pin
Clock Load
Latched
Input
Latch
R
UP
/
4
Jumper options
NOTE:
Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/06/02 Page 4
Preliminary
PLL702-03
Low EMI Peripheral Clock Generator for Notebook PCs
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
T
S
T
A
-65
-40
SYMBOL
V
CC
V
I
V
O
MIN.
MAX.
7
V
CC
+
0.5
V
CC
+
0.5
260
150
85
UNITS
V
V
V
°C
°C
°C
-
0.5
-
0.5
-
0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause
permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional
operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for
INDUSTRIAL grade only.
2. AC Specification
PARAMETERS
Input Frequency (to be set via XTAL_SEL)
SST modulation sweep rate
Output Rise Time
Output Fall Time
Duty Cycle
Duty Cycle 8MHz clock
Max. Absolute Period Jitter
Max. Jitter, cycle to cycle
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
At VDD/2
Long term, No SST
Long term + Short term
45
43
50
50
CONDITIONS
+/- 20ppm accuracy
MIN.
TYP.
24.576
28
MAX.
UNITS
MHz
kHz
1.5
1.5
55
57
150
120
ns
ns
%
%
ps
ps
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/06/02 Page 5
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