PLL702-03 datasheet, PDF - EEWORLD Datasheet

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PLL702-03: DescriptionLow EMI Peripheral Clock Generator for Notebook PCs; File Size99KB，7 Pages; ManufacturerPLL (PhaseLink Corporation)

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PLL702-03 Overview

Low EMI Peripheral Clock Generator for Notebook PCs

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Preliminary

PLL702-03

Low EMI Peripheral Clock Generator for Notebook PCs

FEATURES

•

PIN ASSIGNMENT

Single Low EMI IC to replace multiple crystals and

oscillators on Notebooks and Motherboards (27MHz,

8MHz, 12MHz, 24.576MHz, 25MHz).

Single crystal input: 24.576MHz (accuracy requirement

+/- 20ppm)

Less than 10ppm Frequency Synthesis error, meeting

AC97, IEEE1394, IEEE802 and USB2.0 frequency

precision specification.

27MHz clock with 5 levels of Selectable Spread

Spectrum modulation form +/- 0.5% to +/- 1.5% center.

25MHz clock with double drive strength (Ethernet PHY

and MAC).

24.576MHz clocks for Audio Codec and IEEE1394.

Selectable 12MHz (USB 2.0) or 8MHz (Keyboard

controller).

Dual power source selection for 24.576MHz, 8MHz, and

12MHz.

Available in 16-Pin SOIC or TSSOP.

VDDOSC

XIN

XOUT

VSSOSC

VSSB1

24.576MHz/SST0*

24.576MHz/SST1*

VDDB1

VDDB2

27MHz

VSSB2

8MHz

12MHz/VDD_SEL*

VSS25M

25MHzx2

VDD25M

PLL 702-03

Note:

25MHzx2: double drive strength

*: Bi-directional pin

: Internal pull-down resistor (120k

Ω)

: Tri-level input

Table 1. SPREAD SPECTRUM SELECTION

SST1

SST0

SST Modulation only on

27MHz. (pin 15)

+/- 1.5 %

+/- 1.25 %

+/- 1 %

+/- 0.75 %

+/- 0.5 %

SST OFF (Default)

POWER GROUPS

•

VDDOSC –

VSSOSC: XIN, XOUT, analog core and

digital part.

VDDB1 –

VSSB1: 24.576MHz.

VDDB2 –

VSSB2: 27MHz, 8MHz, and 12MHz.

VDD25M –

VSS25M: 25MHz, (also used for 12MHz,

8MHz when power VDDB2 is not present, and

24.576MHz when power VDDB1 is not present).

•

Notes: M = Do not connect. 1 = Pulled up. 0 = Pulled down.

Table 2. POWER SELECTION TABLE

VDD_SEL

24.576MHz

(pin 7)

VDDB1

VDD25M

12MHz (pin 12)

8MHz (pin 13)

VDDB2

VDD25M

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 10/06/02 Page 1

Preliminary

PLL702-03

Low EMI Peripheral Clock Generator for Notebook PCs

Connecting a bi-directional pin

The PLL702-03 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs

have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can

be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in

order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-

up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin

and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-

directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up

resistor.

Note:

when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor

may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.

For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the

internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the

pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is

recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application

Diagram).

Note:

when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is

in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be

dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is particularly

true when driving 74FXX TTL components.

APPLICATION DIAGRAM: BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP

Internal to chip

VDD

External Circuitry

Power Up

Reset

Output

Bi-directional pin

Clock Load

Latched

Input

Latch

Jumper options

NOTE:

Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 10/06/02 Page 4

PLL702-03 Related Products

	PLL702-03	PLL702-03OC	PLL702-03OI	PLL702-03SC	PLL702-03SI	PLL702-03SM	PLL702-03OM
Description	Low EMI Peripheral Clock Generator for Notebook PCs	Low EMI Peripheral Clock Generator for Notebook PCs	Low EMI Peripheral Clock Generator for Notebook PCs	Low EMI Peripheral Clock Generator for Notebook PCs	Low EMI Peripheral Clock Generator for Notebook PCs	Low EMI Peripheral Clock Generator for Notebook PCs	Low EMI Peripheral Clock Generator for Notebook PCs

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