Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, S
INGLE
-E
NDED
M
ULTIPLEXER
F
EATURES
• 4:1 single-ended multiplexer
• Q nominal output impedance: 7Ω (V
DDO
=3 .3V)
• Maximum output frequency: 250MHz
• Propagation delay: 3ns (maximum), V
DD
= V
DDO
= 3.3V
• Input skew: 225ps (maximum), V
DD
= V
DDO
= 3.3V
• Part-to-part skew: 475ps (maximum), V
DD
= V
DDO
= 3.3V
• Operating supply modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS83054I is a low skew, 4:1, Single-
ended Multiplexer and a member of the
HiPerClockS™
HiPerClockS ™ family of High Performance
Clock Solutions from ICS. The ICS83054I
has four selectable single-ended clock inputs
and one single-ended clock output. The output has a
V
DDO
pin which may be set at 3.3V, 2.5V, or 1.8V, making
the device ideal for use in voltage translation applications.
An output enable pin places the output in a high
impedance state which may be useful for testing or
debug. The device operates up to 250MHz and is pack-
aged in a 16 TSSOP.
IC
S
B
LOCK
D
IAGRAM
CLK0
CLK1
Q
CLK2
CLK3
P
IN
A
SSIGNMENT
Q
nc
OE
CLK3
GND
nc
SEL1
CLK2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DDO
nc
CLK0
nc
V
DD
nc
CLK1
SEL0
ICS83054I
SEL1
SEL0
OE
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
83054AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 3, 2006
1
Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
3
4 , 8,
10, 14
5
7, 9
2, 6, 11, 13, 15
12
16
Name
Q
OE
CLK3, CLK2,
CLK1, CLK0
GND
SEL1, SEL0
nc
V
DD
V
DDO
Type
Output
Input
Input
Power
Input
Unused
Power
Power
Pullup
Description
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Clock select input. See Control Input Function Table.
Pulldown
LVCMOS / LVTTL interface levels.
No connect.
Core and input supply pin.
Output supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 1.89V
V
DDO
= 3.465V
R
OUT
Output Impedance
V
DDO
= 2.625V
V
DDO
= 1.89V
Test Conditions
Minimum
Typical
4
51
51
18
20
30
7
7
10
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Control Inputs
SEL1
SEL0
0
0
0
1
1
1
0
1
Input Selected to Q
CLK0
CLK1
CLK2
CLK3
83054AGI
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2
REV. A JANUARY 3, 2006
Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, S
INGLE
-E
NDED
M
ULTIPLEXER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
40
5
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3. 3
2.5
Maximum
3.465
2.625
40
5
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.71
Typical
3.3
1. 8
Maximum
3.465
1.89
40
5
Units
V
V
mA
mA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
35
5
Units
V
V
mA
mA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
83054AGI
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
1.71
Typical
2.5
1.8
Maximum
2.625
1.89
35
5
Units
V
V
mA
mA
www.icst.com/products/hiperclocks.html
REV. A JANUARY 3, 2006
3
Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK0:CLK3,
SEL0, SEL1
OE
CLK0:CLK3,
SEL0, SEL1
OE
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%; NOTE 1
V
OH
Output HighVoltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 5%; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 5%; NOTE 1
-5
-150
2.6
1.8
V
DD
- 0.3
0.5
0.45
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
Input High Current
I
IL
Input Low Current
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
t
sk(i)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
45
2.4
2.5
2. 7
2.7
55
Test Conditions
Minimum
Typical
Maximum
250
3.0
2.9
225
475
500
55
Units
MHz
ns
ns
ps
ps
ps
%
dB
@ 100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
83054AGI
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 3, 2006
Integrated
Circuit
Systems, Inc.
ICS83054I
4:1, S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
t
sk(i)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
45
2.5
2.6
2.8
2.8
45
Test Conditions
Minimum
Typical
Maximum
250
3.1
3. 0
150
400
500
55
Units
MHz
ns
ns
ps
ps
ps
%
dB
@ 100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
t
sk(i)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low to High; NOTE 1
Propagation Delay, High to Low; NOTE 1
Input Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
45
2.7
2.8
3.2
3.3
50
Test Conditions
Minimum
Typical
Maximum
250
3. 8
3.8
150
475
700
55
Units
MHz
ns
ns
ps
ps
ps
%
dB
@ 100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
83054AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 3, 2006
5
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