Integrated Circuit Systems, Inc.
ICS1893BY-10
General
The ICS1893BY-10 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards. The ICS1893BY-10
supports managed or unmanaged node, repeater, and
switch applications.
The ICS1893BY-10 is intended for MII, Node applications
that require the Auto-MIDIX feature that automatically
corrects crossover errors in plant wiring.
The ICS1893BY-10 incorporates digital signal processing
(DSP) in its Physical Medium Dependent (PMD) sublayer.
As a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100 MHz. With this ICS-patented
technology, the ICS1893BY-10 can virtually eliminate errors
from killer packets.
The ICS1893BY-10 provides a Serial Management Interface
for exchanging command and status information with a
Station Management (STA) entity.
The ICS1893BY-10 Media Dependent Interface (MDI) can
be configured to provide either half- or full-duplex operation
at data rates of 10 MHz or 100 MHz. The MDI configuration
can be established manually (with input pins or control
register settings) or automatically (using the
Auto-Negotiation features). When the ICS1893BY-10
Auto-Negotiation sublayer is enabled, it exchanges
technology capability data with its remote link partner and
automatically selects the highest-performance operating
mode they have in common.
Document Type:
Data Sheet
Document Stage: Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
Features
•
Supports category 5 cables with attenuation in excess of
•
24 dB at 100 MHz
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Low-power, 0.35-micron CMOS (typically 400 mW)
Power-down mode typically 21mW
Single 3.3-V power supply.
Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
10Base-T and 100Base-TX IEEE 802.3 compliant
Highly configurable design supports:
– Node, repeater, and switch applications
– Managed and unmanaged applications
– 10M or 100M half- and full-duplex modes
– Parallel detection
– Auto-negotiation, with Next Page capabilities
– Auto-MDI/MDIX crossover correction
MAC/Repeater Interface can be configured as:
– 10M or 100M Media Independent Interface
– 100M Symbol Interface (bypasses the PCS)
– 10M 7-wire Serial Interface
Clock and crystal supported
Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
Available in Industrial Temperature and Lead-Free
•
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•
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•
ICS1893BY-10 Block Diagram
100Base-T
10/100 MII or
Alternate
MAC/Repeater
Interface
Interface
MUX
PCS
• Frame
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII Serial
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
ICS1893BY-10 Rev A 3/24/04
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
March, 2004
ICS1893BY-10 Data Sheet - Release
Table of Contents
Table of Contents
Section
Title
Page
Revision History
............................................................................................................................. 9
Chapter 1
Abbreviations and Acronyms ......................................................................................... 10
Chapter 2
Conventions and Nomenclature..................................................................................... 12
Chapter 3
Overview of the ICS1893BY-10 ....................................................................................... 14
3.1
100Base-TX Operation ..........................................................................................15
3.2
10Base-T Operation ...............................................................................................15
Chapter 4
4.1
4.1.1
4.1.2
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.5.1
5.6
5.7
5.8
Chapter 6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Operating Modes Overview............................................................................................. 16
Reset Operations ...................................................................................................17
General Reset Operations .....................................................................................17
Specific Reset Operations .....................................................................................18
Power-Down Operations ........................................................................................19
Automatic Power-Saving Operations .....................................................................20
Auto-Negotiation Operations ..................................................................................20
100Base-TX Operations ........................................................................................21
10Base-T Operations .............................................................................................21
Half-Duplex and Full-Duplex Operations ...............................................................21
Auto-MDI/MDIX Crossover .....................................................................................22
Interface Overviews.......................................................................................................... 23
MII Data Interface ..................................................................................................24
100M Symbol Interface ..........................................................................................25
10M Serial Interface ...............................................................................................27
Serial Management Interface .................................................................................29
Twisted-Pair Interface ............................................................................................29
Twisted-Pair Interface ............................................................................................29
Clock Reference Interface .....................................................................................31
Configuration Interface ...........................................................................................33
Status Interface ......................................................................................................34
Functional Blocks............................................................................................................. 36
Functional Block: Media Independent Interface .....................................................37
Functional Block: Auto-Negotiation ........................................................................38
Auto-Negotiation General Process ........................................................................38
Auto-Negotiation: Parallel Detection ......................................................................39
Auto-Negotiation: Remote Fault Signaling .............................................................40
Auto-Negotiation: Reset and Restart .....................................................................40
Auto-Negotiation: Progress Monitor .......................................................................41
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
2
March, 2004
ICS1893BY-10 - Release
Table of Contents
Table of Contents
Section
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10
6.5.11
6.5.12
6.5.13
6.5.14
6.6
6.6.1
6.6.2
Title
Page
Functional Block: 100Base-X PCS and PMA Sublayers ........................................42
PCS Sublayer ........................................................................................................42
PMA Sublayer ........................................................................................................43
PCS/PMA Transmit Modules .................................................................................43
PCS/PMA Receive Modules ..................................................................................44
PCS Control Signal Generation .............................................................................45
4B/5B Encoding/Decoding .....................................................................................45
Functional Block: 100Base-TX TP-PMD Operations .............................................46
100Base-TX Operation: Stream Cipher Scrambler/Descrambler ..........................46
100Base-TX Operation: MLT-3 Encoder/Decoder .................................................46
100Base-TX Operation: DC Restoration ................................................................46
100Base-TX Operation: Adaptive Equalizer ..........................................................47
100Base-TX Operation: Twisted-Pair Transmitter .................................................47
100Base-TX Operation: Twisted-Pair Receiver .....................................................47
Functional Block: 10Base-T Operations ................................................................48
10Base-T Operation: Manchester Encoder/Decoder .............................................48
10Base-T Operation: Clock Synthesis ...................................................................48
10Base-T Operation: Clock Recovery ...................................................................49
10Base-T Operation: Idle .......................................................................................49
10Base-T Operation: Link Monitor .........................................................................49
10Base-T Operation: Smart Squelch .....................................................................50
10Base-T Operation: Carrier Detection .................................................................50
10Base-T Operation: Collision Detection ...............................................................51
10Base-T Operation: Jabber ..................................................................................51
10Base-T Operation: SQE Test .............................................................................51
10Base-T Operation: Twisted-Pair Transmitter .....................................................52
10Base-T Operation: Twisted-Pair Receiver .........................................................52
10Base-T Operation: Auto Polarity Correction .......................................................52
10Base-T Operation: Isolation Transformer ...........................................................52
Functional Block: Management Interface ...............................................................53
Management Register Set Summary .....................................................................53
Management Frame Structure ...............................................................................53
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
3
March, 2004
ICS1893BY-10 Data Sheet - Release
Table of Contents
Table of Contents
Section
Chapter 7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.4
Title
Page
Management Register Set ............................................................................................... 56
Introduction to Management Register Set .............................................................57
Management Register Set Outline .........................................................................57
Management Register Bit Access ..........................................................................58
Management Register Bit Default Values ..............................................................58
Management Register Bit Special Functions .........................................................59
Register 0: Control Register ...................................................................................60
Reset (bit 0.15) ......................................................................................................60
Loopback Enable (bit 0.14) ....................................................................................61
Data Rate Select (bit 0.13) .....................................................................................61
Auto-Negotiation Enable (bit 0.12) .........................................................................61
Low Power Mode (bit 0.11) ....................................................................................62
Isolate (bit 0.10) ......................................................................................................62
Restart Auto-Negotiation (bit 0.9) ..........................................................................62
Duplex Mode (bit 0.8) .............................................................................................63
Collision Test (bit 0.7) ............................................................................................63
IEEE Reserved Bits (bits 0.6:0) .............................................................................63
Register 1: Status Register ....................................................................................64
100Base-T4 (bit 1.15) ............................................................................................64
100Base-TX Full Duplex (bit 1.14) .........................................................................65
100Base-TX Half Duplex (bit 1.13) ........................................................................65
10Base-T Full Duplex (bit 1.12) .............................................................................65
10Base-T Half Duplex (bit 1.11) .............................................................................65
IEEE Reserved Bits (bits 1.10:7) ...........................................................................66
MF Preamble Suppression (bit 1.6) .......................................................................66
Auto-Negotiation Complete (bit 1.5) .......................................................................66
Remote Fault (bit 1.4) ............................................................................................67
Auto-Negotiation Ability (bit 1.3) ............................................................................67
Link Status (bit 1.2) ................................................................................................67
Jabber Detect (bit 1.1) ...........................................................................................68
Extended Capability (bit 1.0) ..................................................................................68
Register 2: PHY Identifier Register ........................................................................69
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
4
March, 2004
ICS1893BY-10 - Release
Table of Contents
Table of Contents
Section
7.5
7.5.1
7.5.2
7.5.3
7.6
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
Title
Page
Register 3: PHY Identifier Register ........................................................................71
OUI bits 19-24 (bits 3.15:10) ..................................................................................71
Manufacturer’s Model Number (bits 3.9:4) .............................................................71
Revision Number (bits 3.3:0) .................................................................................72
Register 4: Auto-Negotiation Register ...................................................................72
Next Page (bit 4.15) ...............................................................................................73
IEEE Reserved Bit (bit 4.14) ..................................................................................73
Remote Fault (bit 4.13) ..........................................................................................73
IEEE Reserved Bits (bits 4.12:10) .........................................................................73
Technology Ability Field (bits 4.9:5) .......................................................................74
Selector Field (Bits 4.4:0)........................................................................................75
Register 5: Auto-Negotiation Link Partner Ability Register ....................................76
Next Page (bit 5.15) ...............................................................................................76
Acknowledge (bit 5.14) ..........................................................................................77
Remote Fault (bit 5.13) ..........................................................................................77
Technology Ability Field (bits 5.12:5) .....................................................................77
Selector Field (bits 5.4:0) .......................................................................................77
Register 6: Auto-Negotiation Expansion Register ..................................................78
IEEE Reserved Bits (bits 6.15:5) ...........................................................................78
Parallel Detection Fault (bit 6.4) .............................................................................79
Link Partner Next Page Able (bit 6.3) ....................................................................79
Next Page Able (bit 6.2) .........................................................................................79
Page Received (bit 6.1) .........................................................................................79
Link Partner Auto-Negotiation Able (bit 6.0) ..........................................................79
Register 7: Auto-Negotiation Next Page Transmit Register ...................................80
Next Page (bit 7.15) ...............................................................................................81
IEEE Reserved Bit (bit 7.14) ..................................................................................81
Message Page (bit 7.13) ........................................................................................81
Acknowledge 2 (bit 7.12) .......................................................................................81
Toggle (bit 7.11) .....................................................................................................81
Message Code Field / Unformatted Code Field (bits 7.10:0) .................................81
Register 8: Auto-Negotiation Next Page Link Partner Ability Register ...................82
Next Page (bit 8.15) ...............................................................................................83
IEEE Reserved Bit (bit 8.14) ..................................................................................83
Message Page (bit 8.13) ........................................................................................83
Acknowledge 2 (bit 8.12) .......................................................................................83
Message Code Field / Unformatted Code Field (bits 8.10:0) .................................83
ICS1893BY-10 Rev A 3/24/04
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
5
March, 2004
Discrete Device
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