PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
Description
The ICS671-03 is a low phase noise, high speed PLL
based, 8 output, low skew zero delay buffer. Based on
ICS’s proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew
outputs at speeds up to 133 MHz at 3.3 V. The
outputs can be generated from the PLL (for zero
delay), or directly from the input (for testing), and can
be set to tri-state mode or to stop at a low level. For
normal operation as a zero delay buffer, any output
clock is tied to the FBIN pin.
ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Clock outputs from 10 to 133 MHz
• Zero input-output delay
• Eight low-skew (<200 ps) outputs
• Device-to-device skew <700 ps
• Low jitter (<200 ps)
• Full CMOS outputs with 25 mA output drive
capability at TTL levels
• 5 V tolerant FBIN and CLKIN pins
• Tri-state mode for board-level testing
• Advanced, low power, sub-micron CMOS process
• 3.3 V operating voltage
• Industrial temperature range of -40 to 85 °C
Block Diagram
2
S2, S1
Control
Logic
CLKA1
CLKA2
CLKA3
CLKIN
CLKA4
Clock
Synthesis
PLL
FBIN
CLKB1
CLKB2
CLKB3
CLKB4
Feedback is shown from CLKB4 for illustration, but may
come from any output.
MDS 671-03 A
1
Revision 072501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com
PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
Pin Assignment
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
16 pin narrow (150 mil) SOIC
Output Clock Mode Select Table
S2
S1
CLKA1:A4
CLKB1:B4
0
0
Tri-state (Note 1)
Tri-state (Note 1)
0
1
Stopped Low
Stopped Low
1
0
Running
Running
1
1
Running
Running
Notes: 1. Outputs are in high impedance state with weak pulldowns.
2. Buffer mode only; not zero delay between input and output.
A & B Source
PLL
none
CLKIN (Note 2)
PLL
PLL Status
ON
OFF
OFF
ON
Pin Descriptions
Number
Name
1
CLKIN
2, 3, 14, 15 CLKA1:A4
4, 13
VDD
5, 12
GND
6, 7, 10, 11 CLKB1:B4
8
S2
9
S1
16
FBIN
Type
I
O
P
P
O
I
I
I
Description
Clock Input. (5 V tolerant)
Clock Outputs A1:A4. See above table. Outputs have weak pulldown resistors.
Power supply. Connect both pins to 3.3 V.
Connect to ground.
Clock Outputs B1:B4. See above table. Outputs have weak pulldown resistors.
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Feedback Input. Connect to any output under normal operation. (5 V tolerant)
Key: I = Input; O = output; P = power supply connection. Outputs have a weak internal pull-down when in tri-state
mode.
External Components
The ICS671-03 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND on pins 13 and 12, as
close to the device as possible. A series termination resistor of 33
Ω
may be used close to each clock output pin to
reduce reflections.
MDS 671-03 A
2
Revision 072501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com
PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
Electrical Specifications
Parameter
Conditions
Minimum Typical
Maximum
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
-0.5
7
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
CLKIN and FBIN Inputs
-0.5
5.5
Electrostatic Discharge
MIL-STD-883
2000
Ambient Operating Temperature
-40
85
Soldering Temperature
Max of 10 seconds
260
Junction temperature
150
Storage temperature
-65
150
DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Operating Voltage, VDD
3.00
3.60
Input High Voltage, VIH
2
Input Low Voltage, VIL
0.8
Output High Voltage, VOH
IOH=-12 mA
2.4
Output Low Voltage, VOL
IOL=12 mA
0.4
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
Operating Supply Current, IDD (Note 2)
No Load, S2=1, S1=1
70
Power Down Supply Current, IDD
CLKIN=0, S2=0, S1=1
1.3
CLKIN=0 (Note 3)
1.3
Short Circuit Current
Each output
±50
Input Capacitance
S2, S1, FBIN
5
AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Input Clock Frequency
See table on page 2
10
133
Output Clock Frequency
See table on page 2
10
133
Output Clock Rise Time, CL=30pF
0.8 to 2.0V
1.5
Output Clock Fall Time, CL=30pF
2.0 to 0.8V
1.25
Output Clock Duty Cycle, VDD=3.3V
At VDD/2
45
50
55
Device to Device Skew, equally loaded
rising edges at VDD/2
700
Output to Output Skew, equally loaded
rising edges at VDD/2
200
Input to Output Skew, FBIN to CLKA4, S1=1, S0 =1
(Note 2)
rising edges at VDD/2
±250
Maximum Absolute Jitter
130
Cycle to Cycle Jitter, 30pF loads
300
PLL Lock Time (Note 4)
1.0
Units
V
V
V
°C
°C
°C
°C
V
V
V
V
V
V
mA
mA
mA
mA
pF
MHz
MHz
ns
ns
%
ps
ps
ps
ps
ps
ms
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz.
3. When there is no clock signal present at CLKIN, the ICS671-03 will enter a power down mode. The PLL is
stopped and the outputs are tri-state.
4. With VDD at a steady state, and valid clocks at CLKIN and FBIN.
MDS 671-03 A
3
Revision 072501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com
PRELIMINARY INFORMATION
ICS671-03
3.3 Volt Zero Delay, Low Skew Buffer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Inches
Symbol
Min
Max
A
0.0532 0.0688
A1
0.0040 0.0098
B
0.0130 0.0200
C
0.0075 0.0098
D
0.3859 0.3937
E
0.1497 0.1574
e
.050 BSC
H
0.2284 0.2440
h
0.0099 0.0195
L
0.0160 0.0500
A
L
Millimeters
Min
Max
1.35
1.75
0.10
0.24
0.33
0.51
0.19
0.24
9.80 10.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.41
1.27
E
INDEX
AREA
H
1
2
h x 45°
D
A1
e
B
C
Ordering Information
Part/Order Number
ICS671M-03I
ICS671M-03IT
Marking
ICS671M-03I
ICS671M-03I
Shipping packaging
tubes
tape and reel
Package
16 pin SOIC
16 pin SOIC
Temperature
-40 to +85 °C
-40 to +85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems,
Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third
parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or
other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the
right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 671-03 A
4
Revision 072501
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • www.icst.com
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