EEWORLDEEWORLDEEWORLD

Part Number

Search

SI5383B-D07502-GM

Description
Clock Synthesizer / Jitter Cleaner 3-PLL Network Synchronizer with 1PPS In/Out
Categorysemiconductor    Analog mixed-signal IC   
File Size918KB,55 Pages
ManufacturerSilicon Laboratories
Download Datasheet Parametric View All

SI5383B-D07502-GM Online Shopping

Suppliers Part Number Price MOQ In stock  
SI5383B-D07502-GM - - View Buy Now

SI5383B-D07502-GM Overview

Clock Synthesizer / Jitter Cleaner 3-PLL Network Synchronizer with 1PPS In/Out

SI5383B-D07502-GM Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerSilicon Laboratories
Product CategoryClock Synthesizer / Jitter Cleaner
PackagingTray
Si5383/84 Rev D Data Sheet
Network Synchronizer Clocks Supporting 1 PPS to 750 MHz
Inputs
The Si5383/84 combines the industry’s smallest footprint and lowest power network syn-
chronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The
Si5383/84 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless
communications systems, and data center switches requiring both traditional and packet
based network synchronization.
The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588
DCO, or a general-purpose PLL for processor/FPGA clocking. The Si5383/84 can also
be used in legacy SETS systems needing Stratum 3/3E compliance. In addition, locking
to a 1 PPS input frequency is available on DSPLL D. The DCO mode provides precise
timing adjustment to 1 part per trillion (ppt). The unique design of the Si5383/84 allows
the device to accept a TCXO/OCXO reference with a wide frequency range, and the ref-
erence clock jitter does not degrade the output performance. The Si5383/84 is configura-
ble via a serial interface and programming the Si5383/84 is easy with ClockBuilder Pro
software. Factory pre-programmed devices are also available.
Applications
• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1
• Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G.
8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813, GR-1244, GR-253 network synchronization
• 1 Hz/1 PPS Clock Multiplier
XTAL
OCXO/
TCXO
XA REFb
OSC
REF
KEY FEATURES
• One or three independent DSPLLs in a
single monolithic IC supporting flexible
SyncE/IEEE 1588 and SETS architectures
• Input frequency range:
• External crystal: 25-54 MHz
• REF clock: 5-250 MHz
• Diff clock: 8 kHz - 750 MHz
• LVCMOS clock: 1 PPS, 8 kHz - 250
MHz
• Output frequency range:
• Differential: 1 PPS, 100 Hz - 718.5 MHz
• LVCMOS: 1 PPS, 100 Hz - 250 MHz
• Ultra-low jitter of less than 150 fs
XB
Si5383/84
IN4
IN3
DSPLL
D
Si5384
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
IN1
IN0
÷FRAC
÷FRAC
I
2
C
FLASH
Control/
Status
DSPLL A
DSPLL C
÷INT
silabs.com
| Building a more connected world.
Si5383
IN2
÷FRAC
Rev. 1.0
Share baby, (*^__^*) hehe...
I just bought this download cable online. I think it’s pretty good. I want to share it with you~! http://item.taobao.com/item.htm?spm=1103BWwE.1-3Y7rP.000000032100076132id=10863150624 &...
FPGA004 Buy&Sell
Purgatory Legend-Asynchronous Reset Synchronous Release Battle
[align=center][align=left][font=新宋体][size=3][color=black]After the previous study, I believe that everyone has fully realized the exquisiteness of [/color][color=black]Verilog[/color][color=black]lang...
梦翼师兄 FPGA/CPLD
Development Trend of Surge Protectors
Surge energy is one of the most important factors that cause damage to power equipment and electronic equipment. The author looks forward to the development trend of metal oxide arresters ,...
frozenviolet Analog electronics
【RT-Thread Reading Notes】3. RT-Thread Study Chapter 4-5 Reading Notes
[i=s]This post was last edited by Media Students on 2019-4-22 22:46[/i] [align=center][size=4][font=微软雅黑][color=darkorchid] [b]【RT-Thread Reading Notes】3. RT-Thread Learning Chapter 4-5 Reading Notes[...
传媒学子 Real-time operating system RTOS
TI University Program Success Story | Professor Sun Xiaozi from Xidian University: School-enterprise collaboration is the best way to combine theory and practice...
[table] [tr][td=671][align=center][p=25, null, left]I am Sun Xiaozi, a teacher at Xidian University. Although I have been retired for many years and have not stood on the podium to teach students for ...
maylove TI Technology Forum

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1254  1695  2223  290  1878  26  35  45  6  38 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号