Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Fully integrated PLL, no external loop filter requirements
•
One differential 3.3V LVPECL output
•
Parallel resonant crystal oscillator interface
•
Output frequency range: 31.25MHz to 700MHz
•
VCO range: 250MHz to 700MHz
•
Parallel interface for programming counter
and output dividers during power-up
•
Serial 3 wire interface
•
RMS Period jitter: 5.5ps (maximum)
•
Cycle-to-cycle jitter: 35ps (maximuml)
•
3.3V supply voltage
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS84329B is a general purpose, single
output high frequency synthesizer and a
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal
to the value of the crystal frequency divided by 16. The VCO
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The output can
be configured to divide the VCO frequency by 1, 2, 4, and 8.
Output frequency steps as small as 125kHz to 1MHz
can be achieved using a 16MHz crystal depending on the
output dividers.
IC
S
B
LOCK
D
IAGRAM
OE
P
IN
A
SSIGNMENT
FOUT
V
CC
25 24 23 22 21 20 19
S_CLOCK
26
27
28
1
18
17
N1
N0
M8
M7
M6
M5
M4
nFOUT
TEST
V
CC
V
EE
V
EE
XTAL_IN
OSC
XTAL_OUT
÷
16
S_DATA
S_LOAD
V
CCA
nc
nc
ICS84329B
16
28-Lead PLCC
15
V Package
2
14
11.6mm x 11.4mm x 4.1mm
3
13
Top View
4
5
6
OE
PLL
PHASE DETECTOR
1
VCO
÷
M
0
÷1
÷2
÷4
÷8
XTAL_IN
12
7
nP_LOAD
8
M0
9 10 11
M1
M2
M3
FOUT
nFOUT
XTAL_OUT
nFOUT
FOUT
TEST
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
V
CC
V
CC
V
CC
V
EE
V
EE
TEST
S_CLOCK
S_DATA
S_LOAD
V
CCA
V
CCA
nc
nc
XTAL_IN
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
nc
N1
N0
M8
M7
M6
M5
M4
ICS84329B
22
32-Lead LQFP
21
Y package
20
7mm x 7mm x 1.4mm
19
Top View
18
17
9 10 11 12 13 14 15 16
XTAL_OUT
OE
nP_LOAD
M0
M1
M2
M3
nc
84329BV
www.icst.com/products/hiperclocks.html
1
REV. B JANUARY 18, 2006
Integrated
Circuit
Systems, Inc.
F
UNCTIONAL
D
ESCRIPTION
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift reg-
ister out) when operating in the parallel input mode. The rela-
tionship between the VCO frequency, the crystal frequency
fxtal
and the M divider is defined as follows:
fVCO = 16 x M
The M value and the required values of M0 through M8
are shown in Table 3B, Programmable VCO Frequency
Function Table. Valid M values for which the PLL will
achieve lock are defined as 250
≤
M
≤
511. The frequency
out is defined as follows: fout fVCO fxtal M
x
=
=
N
N
16
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84329B features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A series-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 250MHz to 700MHz. The output
of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH. The M divide and N output divide
The programmable features of the ICS84329B support two values are latched on the HIGH-to-LOW transition of S_LOAD.
input modes to program the M divider and N output divider. If S_LOAD is held HIGH, data at the S_DATA input is passed
The two input operational modes are parallel and serial.
Fig-
directly to the M divider on each rising edge of S_CLOCK.
ure 1
shows the timing diagram for each mode. In parallel mode The serial mode can be used to program the M and N bits and
the nP_LOAD input is LOW. The data on inputs M0 through test bits T2:T0. The internal registers T2:T0 determine the state
M8 and N0 through N1 is passed directly to the M divider and of the TEST output as follows:
T2
T1
T0
TEST Output
fOUT
0
0
0
Shift Register Out
fOUT
0
0
1
High
fOUT
0
1
0
PLL Reference Xtal ÷ 16
fOUT
0
1
1
VCO ÷ M
fOUT
(non 50% Duty M divider)
1
0
0
fOUT
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
fOUT
1
1
0
S_CLOCK ÷ M
S_CLOCK ÷ N divider
(non 50% Duty Cycle M divider)
1
1
1
fOUT ÷ 4
fOUT
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T2
S
T1
H
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
S_LOAD
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
84329BV
www.icst.com/products/hiperclocks.html
2
REV. B JANUARY 18, 2006
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
Type
Description
Analog supply pin.
Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are disabled and drive differential low:
FOUT = LOW, nFOUT = HIGH. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Name
V
CCA
XTAL_IN,
XTAL_OUT
OE
Power
Input
Input
nP_LOAD
M0, M1, M2, M3,
M4, M5, M6, M7, M8
N0, N1
V
EE
TEST
V
CC
nFOUT, FOUT
S_CLOCK
S_DATA
S_LOAD
Input
Input
Input
Power
Output
Power
Output
Input
Input
Input
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84329BV
www.icst.com/products/hiperclocks.html
3
REV. B JANUARY 18, 2006
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
nP_LOAD
X
L
↑
H
H
H
M
X
Data
Data
X
X
X
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
S_LOAD
X
X
L
L
↑
↓
S_CLOCK
X
X
X
↑
L
L
X
S_DATA
X
X
X
Data
Data
Data
X
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
N
X
Data
Data
X
X
X
H
X
X
L
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
251
252
253
•
•
509
510
511
M Divide
250
251
252
253
•
•
509
510
511
256
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
8
M3
1
1
1
1
•
•
1
1
1
4
M2
0
0
1
1
•
•
1
1
1
2
M1
1
1
0
0
•
•
0
1
1
1
M0
0
1
0
1
•
•
1
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum
250
125
62.5
31.25
Maximum
700
350
175
87.5
84329BV
www.icst.com/products/hiperclocks.html
4
REV. B JANUARY 18, 2006
Integrated
Circuit
Systems, Inc.
ICS84329B
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
-
TO
-3.3V
D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
37.8°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
I
CC
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
125
15
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
M0-M8, N0, N1,
OE, nP_LOAD
Input High Current
S_LOAD,
S_DATA, S_CLOCK
M0-M8, N0, N1,
OE, nP_LOAD
Input Low Current
S_LOAD,
S_DATA, S_CLOCK
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
I
IL
V
OH
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
CC
/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
84329BV
www.icst.com/products/hiperclocks.html
5
REV. B JANUARY 18, 2006
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