Integrated
Circuit
Systems, Inc.
ICS85210-31
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
F
EATURES
•
Dual 1-to-5 HSTL compatible bank outputs
•
2 selectable differential clock input pairs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
•
Maximum output frequency: 650MHz
•
Translates any single ended input signal to
LVHSTL levels with resistor bias on nCLKx inputs
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 350ps (maximum)
•
Propagation delay: 2ns (maximum)
•
3.3V core, 1.8V output operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS85210-31 is a low skew, high perfor-
mance dual 1-to-5 Differential-to-HSTL Fanout
HiPerClockS™
Buffer and a member of the HiPerClock ™
S
family of High Performance Clock Solutions
from ICS. The CLKx, nCLKx pairs can accept
most standard differential input levels. The ICS85210-31 is
characterized to operate from a 3.3V power supply.
Guaranteed output and par t-to-par t skew characteris-
tics make the ICS85210-31 ideal for those clock distri-
bution applications demanding well defined perfor-
mance and repeatability.
ICS
B
LOCK
D
IAGRAM
CLK0
nCLK0
QA0
nQA0
QA1
nQA1
CLK0_EN
D
Q
LE
QA2
nQA2
QA3
nQA3
QA4
nQA4
P
IN
A
SSIGNMENT
nQA0
nQA1
nQA2
V
DDO
V
DDO
QA0
QA1
QA2
32 31 30 29 28 27 26 25
V
DD
CLK0_EN
CLK0
nCLK0
CLK1_EN
CLK1
nCLK1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
DDO
nQB4
QB4
nQB3
QB3
nQB2
QB2
V
DDO
24
23
22
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
ICS85210-31
21
20
19
18
17
CLK1
nCLK1
QB0
nQB0
QB1
nQB1
GND
CLK1_EN
D
Q
LE
QB2
nQB2
QB3
nQB3
QB4
nQB4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
85210AY-31
www.icst.com/products/hiperclocks.html
1
REV. B MARCH 19, 2004
Integrated
Circuit
Systems, Inc.
ICS85210-31
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Type
Power
Pullup
Input
Input
Pullup
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pullup
Pullup
Pullup
Description
Core supply pin.
Synchronizing clock enable.
Inver ting differential clock input.
Synchronizing clock enable.
Inver ting differential clock input.
Power supply ground.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Pulldown Non-inver ting differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9, 16,
25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
DD
CLK0_EN
CLK0
nCLK0
CLK1_EN
CLK1
nCLK1
GND
V
DDO
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Pulldown Non-inver ting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
85210AY-31
www.icst.com/products/hiperclocks.html
2
REV. B MARCH 19, 2004
Integrated
Circuit
Systems, Inc.
ICS85210-31
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Outputs
QA0:QA4, QB0:QB4
Disabled; LOW
nQA0:QA4, nQB0: nQB4
Disabled; HIGH
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0_EN, CLK1_EN
0
1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs
as described in Table 3B.
Disabled
Enabled
nCLK0, nCLK1
CLK0, CLK1
CLK0_EN,
CLK1_EN
nQA0:nQA4,
nQB0:nQB4
QA0:QA4,
QB0:QB4
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK0 or CLK1
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK0 or nCLK1
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA0:QA4,
nQA0:nQA4,
QB0:QB4
nQB0:nQB4
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
85210AY-31
www.icst.com/products/hiperclocks.html
3
REV. B MARCH 19, 2004
Integrated
Circuit
Systems, Inc.
ICS85210-31
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.4V
TO
2.0V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Input Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
No Load
0
Test Conditions
Minimum
3.135
1.4
Typical
3.3
1.8
Maximum
3.465
2.0
120
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.4V
TO
2.0V, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0_EN, CLK1_EN
CLK0_EN, CLK1_EN
CLK0_EN, CLK1_EN
CLK0_EN, CLK1_EN
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.4V
TO
2.0V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLKx and nCLKx is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
85210AY-31
www.icst.com/products/hiperclocks.html
4
REV. B MARCH 19, 2004
Integrated
Circuit
Systems, Inc.
ICS85210-31
L
OW
S
KEW
, D
UAL
, 1-
TO
-5
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
Test Conditions
Minimum
1
0
40% x (V
OH
- V
OL
) + V
OL
0.6
Typical
Maximum
1.4
0.4
60% x (V
OH
- V
OL
) + V
OL
1.1
Units
V
V
V
V
T
ABLE
4D. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.4V
TO
2.0V, T
A
= 0°C
TO
70°C
Symbol Parameter
Output High Voltage;
V
OH
NOTE 1
Output Low Voltage;
V
OL
NOTE 1
V
OX
V
SWING
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.4V
TO
2.0V, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
30% to 70% @ 50MHz
300
IJ 650MHz
1.4
Test Conditions
Minimum
Typical
Maximum
650
2
50
350
700
53
Units
MHz
ns
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
47
All parameters measured at 400MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85210AY-31
www.icst.com/products/hiperclocks.html
5
REV. B MARCH 19, 2004
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