PA7536 datasheet, PDF - EEWORLD Datasheet

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PA7536: DescriptionPEEL Array-TM Programmable Electrically Erasable Logic Array; File Size239KB，10 Pages; ManufacturerAnachip; Websitehttp://www.anachip.com/

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PA7536 Overview

PEEL Array-TM Programmable Electrically Erasable Logic Array

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PA7536 PEEL Array™

Programmable Electrically Erasable Logic Array

Versatile Logic Array Architecture

- 12 I/Os, 14 inputs, 36 registers/latches

- Up to 36 logic cell output functions

- PLA structure with true product-term sharing

- Logic functions and registers can be I/O-buried

Ideal for Combinatorial, Synchronous and

Asynchronous Logic Applications

- Integration of multiple PLDs and random logic

- Buried counters, complex state-machines

- Comparators, decoders, multiplexers and

other wide-gate functions

High-Speed Commercial and Industrial Versions

- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (f

MAX

)

- Industrial grade available for 4.5 to 5.5V V

and

-40 to +85 °C temperatures

CMOS Electrically Erasable Technology

- Reprogrammable in 28-pin DIP, SOIC and PLCC

packages

Flexible Logic Cell

- Up to 3 output functions per logic cell

- D,T and JK registers with special features

- Independent or global clocks, resets, presets,

clock polarity and output enables

- Sum-of-products logic for output enables

Development and Programmer Support

- Anachip WinPLACE Development Software

- Fitters for ABEL and other software

- Programming support by popular third-party

programmers

General Description

The PA7536 is a member of the Programmable Electrically

Erasable Logic (PEEL™) Array family based on ICT’s

CMOS EEPROM technology. PEEL™ Arrays free

designers from the limitations of ordinary PLDs by

providing the architectural flexibility and speed needed for

today’s programmable logic designs. The PA7536 offers a

versatile logic array architecture with 12 I/O pins, 14 input

pins and 36 registers/latches (12 buried logic cells, 12

Input registers/latches and 12 buried registers/latches). Its

logic array implements 50 sum-of-products logic functions

that share 64 product terms. The PA7536’s logic and I/O

cells (LCCs, IOCs) are extremely flexible offering up to

three output functions per cell (a total of 36 for all 12 logic

cells). Cells are configurable as D, T, and JK registers with

independent or global clocks, resets, presets, clock

polarity, and other special features, making the PA7536

suitable for a variety of combinatorial, synchronous and

asynchronous logic applications. The PA7536 offers pin

compatibility and super-set functionality to popular 28-pin

PLDs, such as the 26V12. Thus, designs that exceed the

architectures of such devices can be expanded upon. The

PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)

and 83.3MHz (f

MAX

) at moderate power consumption

105mA (75mA typical). Packaging includes 28-pin DIP,

SOIC, and PLCC (see Figure 1). Development and

programming support for the PA7536 is provided by

Anachip and popular third-party development tool

manufacturers.

Figure 1. Pin Configuration

I/CLK1

VCC

I/CLK2

I/O

GND

I/O

I/CLK1

VCC

I/CLK2

I/O

GND

I/O

Figure 2. Block Diagram

2 Input/

Global Clock Pins

Global

Cells

76 (38X2)

Array Inputs

true and

com plement

Buried

logic

Logic functions

to I/O cells

I/O

Cells

(IOC)

12 I/O Pins

12 Input Pins

Input

Cells

(INC)

S O IC

I/CLK1

I/CLK2

I/O

I/CL K1

In p ut C ells

I/O Ce lls

G lo ba l Ce lls

I/CL K2

I/O

G ND

I/O

L og ic Co ntro l C e lls

I/O

L og ic

Array

D IP

VCC

12 13 14 15 16 17 18

1 28 27 26

I/O

GND

I/O

Logic

Control

Cells

(LCC)

VC C

08 -16 -0 01A

2 sum terms

3 product term s

for Global Cells

48 sum term s

(four per LCC)

12 Logic Control Cells

up to 3 output functions per cell

(36 total output functions possible)

I/O

PLCC

P A7536

0 8-1 6-0 02 A

04-02-052A

PA7536 Related Products

	PA7536	PA7536J-15	PA7536P-15	PA7536S-15	PA7536PI-15	PA7536SI-15	PA7536JI-15
Description	PEEL Array-TM Programmable Electrically Erasable Logic Array	PEEL Array-TM Programmable Electrically Erasable Logic Array	PEEL Array-TM Programmable Electrically Erasable Logic Array	PEEL Array-TM Programmable Electrically Erasable Logic Array	PEEL Array-TM Programmable Electrically Erasable Logic Array	PEEL Array-TM Programmable Electrically Erasable Logic Array	PEEL Array-TM Programmable Electrically Erasable Logic Array
Is it Rohs certified?	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	-	Anachip	Anachip	Anachip	Anachip	Anachip	-
Reach Compliance Code	-	unknow	unknow	unknow	unknow	unknow	unknow

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