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590AC155M025DGR

Description
Standard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS)
CategoryPassive components   
File Size394KB,15 Pages
ManufacturerSilicon Laboratories
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590AC155M025DGR Overview

Standard Clock Oscillators Single Frequency XO, OE Pin 2 (OE Pin 1 CMOS)

590AC155M025DGR Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerSilicon Laboratories
Product CategoryStandard Clock Oscillators
Frequency155.025 MHz
Frequency Stability30 PPM
Load Capacitance15 pF
Operating Supply Voltage3.3 V
Supply Voltage - Min2.97 V
Supply Voltage - Max3.63 V
Output FormatLVPECL
Termination StyleSMD/SMT
Package / Case7 mm x 5 mm
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Length7 mm
Width5 mm
Height1.65 mm
PackagingBox
Current Rating110 mA
TypeCrystal Oscillator
Duty Cycle - Max55 %
S i 5 9 0 / 5 91
1 ps M
AX
J
I T T E R
C
RYSTAL
O
SC ILLA TOR
(XO)
(10 M H
Z TO
810 MH
Z
)
Features
Available with any-frequency output
frequencies from 10 to 810 MHz
3rd generation DSPLL
®
with superior
jitter performance: 1 ps max jitter
Better frequency stability than SAW-
based oscillators
Internal fundamental mode crystal
ensures high reliability
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry Standard 5x7 and
3.2x5 mm packages
Pb-free/RoHS-compliant
–40 to +85 ºC operating
temperature range
Si5602
Applications
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
Ordering Information:
See page 7.
Test and measurement
Storage
FPGA/ASIC clock generation
Description
The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide a low jitter clock at high frequencies. The Si590/591 supports any
frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique
crystal is required for each output frequency, the Si590/591 uses one fixed
crystal to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The
Si590/591 IC based XO is factory configurable for a wide variety of user
specifications including frequency, supply voltage, output format, and
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si590 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
NC
CLK
Functional Block Diagram
V
DD
CLK– CLK+
17 k
*
Fixed
Frequency
XO
Si590 (CMOS)
Any-rate
10–810 MHz
DSPLL
®
Clock
Synthesis
V
DD
CLK–
CLK+
OE
OE
NC
GND
1
2
3
6
5
4
17 k
*
GND
*Note: Output Enable High/Low Options Available – See Ordering Information
Si591 (LVDS/LVPECL/CML)
Rev. 1.1 12/17
Copyright © 2017 by Silicon Laboratories
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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