PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843011C
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
F
EATURES
•
One differential 3.3V LVPECL output
•
Crystal oscillator interface designed for 26.5625MHz
18pF parallel resonant crystal
•
Output frequency: 106.25MHz or 100MHz
•
VCO range: 560MHz - 680MHz
•
RMS phase jitter @ 100MHz, using a 25MHz crystal
(637kHz - 10MHz): 0.29ps (typical)
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS843011C is a Fibre Channel Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from ICS.
The ICS843011C uses a 26.5625MHz crystal to
synthesize 106.25MHz or a 25MHz crystal to
synthesize 100MHz. The ICS843011C has excellent <1ps
phase jitter performance, over the 637kHz – 10MHz
integration range. The ICS843011C is packaged in a small
8-pin TSSOP, making it ideal for use in systems with limit-
ed board space.
IC
S
F
REQUENCY
T
ABLE
Crystal (MHz)
26.5625
25
Output Frequency (MHz)
106.25
100
B
LOCK
D
IAGRAM
XTAL_IN
P
IN
A
SSIGNMENT
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
OSC
XTAL_OUT
÷6
Q
nQ
V
CCA
V
EE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
CC
Q
nQ
nc
M = ÷24 (fixed)
ICS843011C
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843011CG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843011C
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
Type
Power
Power
Input
Description
Analog supply pin.
Negative supply pin.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
No connect.
Differential clock outputs. LVPECL interface levels.
Core supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3,
4
5
6, 7
8
Name
V
CCA
V
EE
XTAL_OUT,
XTAL_IN
nc
nQ, Q
V
CC
Unused
Output
Power
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
843011CG
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 25, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843011C
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
101.7°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
I
CCA
I
EE
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
included in I
EE
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
10
68
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
3B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
25
Test Conditions
Minimum
Typical
Fundamental
26.5625
50
7
MH z
Ω
pF
Maximum
Units
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
F
OUT
t
jit(Ø)
t
R
/ t
F
odc
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
106.25MHz;
Integration Range: 637kHz - 10MHz
100MHz;
Integration Range: 637kHz - 10MHz
20% to 80%
Test Conditions
Minimum
93.33
0.29
0.29
400
50
Typical
Maximum
113.33
Units
MHz
ps
ps
ps
%
NOTE 1: Please refer to the Phase Noise Plot.
843011CG
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 25, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843011C
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
Phase Noise Plot
Noise Power
V
CC
Qx
SCOPE
LVPECL
nQx
Phase Noise Mask
V
EE
f
1
Offset Frequency
f
2
-1.3V ± 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
nQ
Q
t
PW
t
PERIOD
80%
Clock
Outputs
x 100%
80%
V
SW I N G
20%
t
R
t
F
20%
odc =
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
843011CG
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 25, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843011C
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843011C provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
and V
CCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA
pin.
3.3V
V
CC
.01μF
10Ω
V
CCA
.01μF
10μF
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843011C has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2
below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
843011CG
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 25, 2006
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