PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
F
EATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS844004I-01 is a 4 output LVDS Synthesizer
optimized to generate Ethernet reference clock
HiPerClockS™
frequencies and is a member of the HiPerClocks
TM
family of high performance clock solutions from
ICS. Using a 25MHz 18pF parallel resonant crystal,
the following frequencies can be generated based on the 2
frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and
62.5MHz. The ICS844004I-01 uses ICS’ 3
rd
generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844004I-01 is packaged in a small 24-
pin TSSOP package.
ICS
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL1 F_SEL0
0
0
1
1
0
1
0
1
M Divider
Value
25
25
25
25
N Divider
Value
4
5
10
Not Used
M/N Divider
Value
6.25
5
2.5
Output
Frequency
(25MHz Ref.)
156.5
125
62.5
Not Used
P
IN
A
SSIGNMENT
nQ1
Q1
V
DD
o
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
V
DD
nXTAL_SEL
TEST_CLK
GND
XTAL_IN
XTAL_OUT
ICS844004I-01
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
Pulldown
25MHz
2
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q0
1
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
nQ0
Q1
nQ1
TEST_CLK
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
0
Q2
nQ2
M = 25 (fixed)
Q3
nQ3
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQ1, Q1
V
DDO
Q0, nQ0
MR
Type
Output
Power
Ouput
Input
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
7
8
9
10, 12
11, 18
13, 14
15, 19
16
17
20, 21
23, 24
nPLL_SEL
nc
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
GND
TEST_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
844004AGI-01
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
10mA
15mA
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
TBD
TBD
TBD
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
TBD
TBD
TBD
Maximum
2.625
2.625
2.625
Units
V
V
V
mA
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%
OR
2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465 or 2.5V
V
DD
= 3.465V or 2.5V,
V
IN
= 0V
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
-150
µA
844004AGI-01
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
3D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
40
1.4
50
Maximum
Units
mV
mV
V
mV
T
ABLE
3E. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
350
40
1.2
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
22.4
Test Conditions
Minimum
Typical
25
Maximum
27.2
50
7
1
Units
MH z
Ω
pF
mW
Fundamental
844004AGI-01
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 15, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS844004I-01
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
Typical
156.5
125
62.5
TBD
156.25MHz, (1.875MHz - 20MHz)
0.41
0.44
0.47
450
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
t
sk(o)
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, TA = -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
t
R
/ t
F
20% to 80%
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
Typical
156.5
125
62.5
TBD
0.41
0.44
0.47
480
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
t
sk(o)
t
jit(Ø)
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 15, 2005
ARM Technology
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