CN8223
ATM Transmitter/Receiver with UTOPIA Interface
The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a
single-access ATM service termination for User-to-Network (UNI) and
Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
Specification 94/0317; Bellcore Specifications TR-TSV-000772, TR-TSV-000773,
TR-NWT-000253, and T1S1/92-185; ITU Recommendations I.432, G.707, G.751,
G.832, and Q.921; and ETSI prETS 300 213 and 300 214. Both Customer Premise
Equipment (CPE) and switching system interface functions are provided. The CN8223
provides DS1, E1, DS3, E3, E4, STS-1, and STS-3c (and STM-1) ATM cell alignment
functions. The system interface is via a parallel FIFO port or UTOPIA interface. In
addition, the CN8223 terminates the operations and maintenance flows F1, F2, and F3.
The CN8223 provides four FIFO port interfaces and one UTOPIA interface. Each
receiver port can be programmed with a particular Virtual Channel Identifier/Virtual
Path Identifier (VCI/VPI) address for message routing. VCI/VPI pages can also be
selected via masking registers.
The microprocessor can set control registers for insertion of selected header fields
by the transmitter on an individual port basis. The microprocessor can also control
insertion of all overhead and can insert errors in selected fields for test equipment
applications.
Distinguishing Features
•
Integrates 7 line framers with ATM
layer processing according to ATM
Forum UNI and NNI Specifications
UTOPIA Level 1 interface
Internal framers for DS3, E3 (G.751,
G.832), E4 (G.832), STS-1, STS-3c,
STM-1
PLCP and G.804 HEC cell alignment
for all data rates from 1.544 Mbps to
155 Mbps
Direct interface to TAXI
TM
or external
T1/E1 framers
ATM and SMDS cell modes
4 FIFO ports with header screening,
formatting, and transmit priority
controls
Idle cells generated and screened
Statistics counts latched on
one-second intervals
Error detection and insertion
Option insertion or generation of all
line and cell overhead
Serial or parallel line interface
Available evaluation module
reference design and software
Supports Automatic Protection
Switching (APS)
•
•
•
•
•
•
•
•
•
•
•
•
Functional Block Diagram
Microprocessor
Address
7
Data
Bus
8
Cell
FIFO
Microprocessor
Data
8
16
HDLC
Data
Link
Line Overhead
•
8
Port
Control
4-Port
FIFO
Interface
Microprocessor
Interface
52 Control Registers
28 Status Registors
Applications
8
UTOPIA
or FIFO
Interface
8
Framers
Cell
Generation
TX
Rate
Control
8
Cell
Alignment
8
HEC or
PLCP
DS3
E3 (G.751)
E3 (G.832)
STS-1
E4 (G.832)
STS-3c
STM-1
TAXI
8
8223_042
1
•
•
•
•
WAN equipment
ATM switches
Test equipment
ATM routers and hub
ATM
UNI
1
8
Header
Filter
Cell
Validation
ATM Layer
Physical Framing
Data Sheet
100046C
March 8, 2000
Ordering Information
Generic Part
Number
Bt8222EPFE
Bt8222EPFF
CN8223EPF
Operating
Temperature
–40
°
C to 85
°
C
–40
°
C to 85
°
C
–40
°
C to 85
°
C
Package
Description
160-pin PQFP
160-pin PQFP
160-pin PQFP
Part Number
28222-13
28222-14
28233-11
Reduced Features
—
—
The CN8223 is based on the Bt8222
device. The only change from the
Bt8222 to the CN8223 is the TTL
I/O pad ring. The I/O structure
allows the CN8223 to function in a
3.3/5 V environment. No new
features, errata fixes, etc., have
been added to the CN8223 other
than TTL threshold inputs.
© 1999, 2000,
Conexant Systems, Inc.
All Rights Reserved.
Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are
provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no
responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at
any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to its specifications and product descriptions.
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100046C
Conexant
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
1.0
Product Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
Block Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
CN8223 Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.4
1.4.1
1.4.2
1.4.3
1.5
1.5.1
1.5.2
1.5.3
1.6
1.7
1.8
1.9
Internal Framers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UTOPIA Port
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Parity Protection
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test and Diagnostic Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microprocessor Interface Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3
1-3
1-4
1-4
1-4
Line Framing Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Interfaces
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Line Loopback
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
BIP-8 Code
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Alarm Detection/Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Cell Generation Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Tx Rate Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Cell Validation Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
UTOPIA Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
FIFO Ports
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
ATM Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
ATM Cell Processing Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
FIFO Port/UTOPIA Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Line Interface Applications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
CN8223 Versions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
CN8223 Applications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.8.1
CN8223 as a DS3 or E3 G.751 Framer without ATM Cell Delineation
. . . . . . . . . . . . . . . . 1-16
Logic Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.10 Pin Definitions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
10046C
Conexant
iii
Table of Contents
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.0
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Microprocessor Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1
2.1.2
2.2
2.2.1
2.2.2
8/16-Bit Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Interrupts.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Internally Framed Transmit Line Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1.1
High-Speed PECL Transmit Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Internally Framed Receive Line Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.2.1
High-Speed PECL Receive Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.2.2
Receiver Framing Operation.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Externally Framed Transmit Line Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Externally Framed Receive Line Interface.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Internal DS3 Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Internal G.832 E3/E4 Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Internal G.751 E3 Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
STS-1 and STS-3c/STM-1 Modes
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Transmit Framing Overhead Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Receive Framing Overhead Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Status and Counter Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Alarm Signal Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Alarm Detection
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
TAXI Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Transmit Parallel Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Receive Parallel Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Cell Generation for Transmit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1.1
CELL_GEN_x Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.1.2
Cell Generation Status and Status Interrupts for Transmit
. . . . . . . . . . . . . . .
Cell Validation for Receive
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2.1
HEC Alignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2.2
CELL_VAL Control Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.2.3
Interrupts and Status Counters for Cell Validation
. . . . . . . . . . . . . . . . . . . . .
PLCP Cell Generation for Transmit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCP Cell Validation for Receive
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6.4.1
PLCP Status
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLCP Transmit/Receive Synchronization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Framers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.5
2.5.1
2.5.2
2.5.3
2.6
2.6.1
Overhead Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Status and Alarms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Parallel Line Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
ATM Cell Processing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.6.2
2.6.3
2.6.4
2.6.5
2-26
2-27
2-28
2-29
2-30
2-30
2-32
2-33
2-35
2-35
2-36
iv
Conexant
100046C
CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.7
Table of Contents
FIFO Port/UTOPIA Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2.7.1
2.7.2
2.7.3
2.7.4
FIFO Interface Inputs and Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Transmit Port Priority Mechanism
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Transmit Rate Shaping Control
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Receive Port Addressing.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
2.7.4.1
Header Screening
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
2.7.4.2
Output Screening
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
UTOPIA Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
FEAC Channel Transmitter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
FEAC Channel Receiver
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
HDLC Data Link Transmitter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
2.8.3.1
Sending a Message
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2.8.3.2
Aborting a Message
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
2.8.3.3
Transmitter Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47
2.8.3.4
Transmitter Control Example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
HDLC Data Link Receiver
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
2.8.4.1
Receiver Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
2.8.4.2
Receiver Interrupts
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Receiver Response Example
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
2.7.5
2.8
2.8.1
2.8.2
2.8.3
FEAC Channel and HDLC Data Link Programming
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
2.8.4
2.8.5
3.0
Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
3.2
3.3
Registers Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Control Register Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Configuration Control Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
0x00—CONFIG_1 (Configuration Control Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
0x01—CONFIG_2 (Configuration Control Register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
0x02—CONFIG_3 (Configuration Control Register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
0x29—CONFIG_4 (Configuration Control Register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
0x31—CONFIG_5 (Configuration Control Register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
0x2B—UTOPIA_1 (Utopia Port Control Register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
0x2C—UTOPIA_2 (Utopia Port Control Register 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.4
Transmit Control Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
0x03—TXFEAC_ERRPAT (Transmit FEAC/Error Pattern Register) . . . . . . . . . . . . . . . . . . . . . . . . .
0x60—DL_CTRL_STAT (HDLC Data Link Control and Status Register) . . . . . . . . . . . . . . . . . . . . .
0x04–0x07—CELL_GEN_x (Cell Generation Control Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x08—TX_RATE_23 (Transmit Rate Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x09—TX_RATE_01 (Transmit Rate Control Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0A—TX_IDLE_12 (Transmit Idle Header Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0B—TX_IDLE_34 (Transmit Idle Header Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x2A—IDLE_PAY (Transmit Idle Cell Payload Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x0C–0x13—TX_HDRx_12, TX_HDRx_34 (Transmit Header Registers) . . . . . . . . . . . . . . . . . . . .
3-14
3-15
3-16
3-17
3-17
3-17
3-17
3-18
3-18
100046C
Conexant
v