PRODUCT SPECIFICATION
PE3339
Product Description
Peregrine’s PE3339 is a high performance integer-N PLL
capable of frequency synthesis up to 3.0 GHz. The
superior phase noise performance of the PE3339 makes
it ideal for applications such as wireless local loop
basestations, LMDS systems and other demanding
terrestrial systems.
The PE3339 features a 10/11 dual modulus prescaler,
counters, phase detector and a charge pump as shown
in Figure 1. Counter values are programmable through a
three wire serial interface.
Fabricated in Peregrine’s patented UTSi® (Ultra Thin
Silicon) CMOS technology, the PE3339 offers excellent
RF performance with the economy and integration of
conventional CMOS.
3.0 GHz Integer-N PLL for Low
Phase Noise Applications
Features
•
3.0 GHz operation
•
÷10/11 dual modulus prescaler
•
Internal phase detector with
charge pump
•
Serial programmable
•
Low power
⎯
23 mA at 3 V
•
Ultra-low phase noise
•
Available in 20-lead TSSOP
Figure 1. Block Diagram
F
in
F
in
Prescaler
10/11
Main
Counter
13
Sdata
Primary
20-bit
20
Latch
Secon-
dary
20-bit
Latch
PD_U
20
20
Phase
Detector
PD_D
Charge
Pump
CP
6
f
r
6
R Counter
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Copyright
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Peregrine Semiconductor Corp. 2004
Page 1 of 12
PE3339
Advance Information
Figure 2. Pin Configuration
V
DD
Enh
S_WR
Sdata
Sclk
GND
FSELS
E_WR
V
DD
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
f
r
GND
N/C
CP
V
DD
Dout
LD
Cext
GND
F
in
F
in
10
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
V
DD
Enh
S_WR
Sdata
Sclk
GND
FSELS
E_WR
V
DD
F
in
F
in
GND
Cext
LD
Dout
V
DD
Type
(Note 1)
Input
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 k
Ω
pull-up
resistor.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
Binary serial data input. Input data entered MSB first.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
Ground.
Input
Input
(Note 1)
Input
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 k
Ω
pull-down resistor.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement
register on the rising edge of Sclk. Internal 70 k
Ω
pull-down resistor.
Same as pin 1.
Prescaler input from the VCO. Max frequency input is 3.0 GHz.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50
Ω
resistor to the ground plane.
Ground.
Output
Output,
OD
Output
(Note 1)
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 k
Ω
series resistor. Connecting Cext to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
Data out function, Dout, enabled in enhancement mode.
Same as pin 1.
File No. 70/0048~02A
|
Copyright
©
Peregrine Semiconductor Corp. 2004
UTSi
®
CMOS RFIC SOLUTIONS
Page 2 of 12
PE3339
Advance Information
Pin No.
17
18
19
20
Note 1:
Pin Name
CP
NC
GND
f
r
Type
Output
Output
Description
Charge pump current is sourced when f
c
leads f
p
and sinked when f
c
lags f
p
.
No connection.
Ground.
Input
Reference frequency input.
V
DD
pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level.
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Electrostatic Discharge (ESD) Precautions
Max
4.0
V
DD
+ 0.3
+10
+10
150
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Units
V
V
mA
mA
°
C
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°
C
Table 4. ESD Ratings
Symbol
V
ESD
Parameter/Conditions
ESD voltage human body
model (Note 1)
Level
1000
Units
V
Note 1:
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
PEREGRINE SEMICONDUCTOR CORP.
®
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Copyright
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Peregrine Semiconductor Corp. 2004
Page 3 of 12
PE3339
Advance Information
Table 5. DC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
Operational supply current;
Prescaler enabled
High level input voltage
Low level input voltage
High level input current
Low level input current
Conditions
V
DD
= 2.85 to 3.15 V
Min
Typ
23
Max
35
Units
mA
V
Digital Inputs: S_WR, Sdata, Sclk
V
IH
V
IL
I
IH
I
IL
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-1
0.7 x V
DD
0.3 x V
DD
+1
V
µ
A
µ
A
Digital Inputs: Enh (contains a 70 k
Ω
pull-up resistor)
V
IH
V
IL
I
IH
I
IL
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
0.7 x V
DD
0.3 x V
DD
+1
V
V
µ
A
µ
A
Digital Inputs: FSELS, E_WR (contains a 70 k
Ω
pull-down resistor)
V
IH
V
IL
I
IH
I
IL
High level input voltage
Low level input voltage
High level input current
Low level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-1
0.7 x V
DD
0.3 x V
DD
+100
V
V
µ
A
µ
A
Reference Divider input: f
r
I
IHR
I
ILR
High level input current
Low level input current
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
+100
µ
A
µ
A
Counter output: Dout
V
OLD
V
OHD
V
OLC
V
OHC
V
OLLD
I
CP
– Source
I
CP
– Sink
I
CPL
I
CP
– Source
VS.
I
CP
Sink
I
CP VS.
V
CP
Output voltage LOW
Output voltage HIGH
Output voltage LOW, Cext
Output voltage HIGH, Cext
Output voltage LOW, LD
Drive current
Drive current
Leakage current
Sink vs. source mismatch
Output current magnitude variation vs. voltage
I
out
= 6 mA
I
out
= -3 mA
I
out
= 0.1 mA
I
out
= -0.1 mA
I
out
= 1 mA
V
CP
= V
DD
/ 2
V
CP
= V
DD
/ 2
1.0 V < V
CP
< V
DD
– 1.0 V
V
CP
= V
DD
/ 2, T
A
= 25
°
C
1.0 V < V
CP
< V
DD
– 1.0 V T
A
= 25
°
C
-2.6
1.4
-1
-2
2
V
DD
- 0.4
0.4
-1.4
2.6
1
15
15
V
DD
- 0.4
0.4
0.4
V
V
V
V
V
mA
mA
µ
A
Lock detect outputs: (Cext, LD)
Charge Pump output: CP
%
%
Copyright
©
Peregrine Semiconductor Corp. 2004
File No. 70/0048~02A
|
UTSi
®
CMOS RFIC SOLUTIONS
Page 4 of 12
PE3339
Advance Information
Table 6. AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
F
in
P
Fin
F
in
P
Fin
Reference Divider
f
r
P
fr
Phase Detector
f
c
Comparison frequency
(Note 3)
20
MHz
SSB Phase Noise (F
in
= 1.3 GHz, f
r
= 10 MHz, f
c
= 1.25 MHz, LBW = 70 kHz, V
DD
= 3.0 V, Temp = -40
°
C
)
100 Hz Offset
1 kHz Offset
Note 1:
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Operating frequency
Input level range
Operating frequency
Input level range
Operating frequency
Reference input power (Note 2)
Conditions
(Note 1)
Min
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Latches (see Figures 3, 4, 5)
30
30
10
10
30
30
30
30
30
500
External AC coupling
-5
50
External AC coupling
(Note 3)
Single ended input
-2
-5
3000
5
300
5
100
Main Divider (Including Prescaler)
MHz
dBm
MHz
dBm
MHz
dBm
Main Divider (Prescaler Bypassed)
-75
-85
dBc/Hz
dBc/Hz
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Note 2:
Note 3:
PEREGRINE SEMICONDUCTOR CORP.
®
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Copyright
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Peregrine Semiconductor Corp. 2004
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