Product Specification
PE3513
Product Description
The PE3513 is a high-performance static UltraCMOS™
prescaler with a fixed divide ratio of 8. Its operating frequency
range is DC to 1500 MHz. The PE3513 operates on a nominal
3 V supply and draws only 8 mA. The input and output
interfaces support both AC-coupled, low-Z RF as well as direct
connection to low voltage positive logic devices. It is packaged
in a small 6-lead SC-70 and is ideal for frequency scaling
solutions
The PE3513 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
1500 MHz Low Power UltraCMOS™
Divide-by-8 Prescaler
Features
•
DC to 1500 MHz operation
•
Fixed divide ratio of 8
Figure 1. Functional Schematic Diagram
IN
Pre-Amp
CLK QB
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
Ω
)
V
DD
= 3.0 V, -40° C
≤
T
A
≤
85° C, unless otherwise specified
BS
Parameter
Conditions
DC <
Fin
≤
1000 MHz (Note 1)
1000 MHz < Fin
≤
1500
DC < Fin
≤
1500 MHz
O
CLK QB
CLK QB
Output
Buffer
D
Q
D
Q
D
LE
6-lead SC70
Q
OUT
Minimum
2.85
Supply Voltage
Supply Current
O
Input Frequency (F
in
)
DC
-10
-3
2
Input Power (P
in
)
Output Power (P
out
)
Note 1:
CMOS logic levels can be used to drive the reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. The
input edge rate should be faster than 80mV/ns from DC - 10 MHz.
Document No. 70-0108-06
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TE
@ 3V
•
RF or LV Digital Interface
•
Low-power consumption: 8 mA typical
•
Ultra-small package: 6-lead SC-70
Figure 2. Package Type
Typical
3.0
8
Maximum
3.15
12
1500
+10
Units
V
mA
MHz
dBm
dBm
dBm
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
PE3513
Product Specification
Table 2. DC Electrical Characteristics (-40° C
≤
T
A
≤
85° C)
Symbol
V
IH
V
IL
V
OH
V
OL
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Condition
2.7 V
≤
V
DD
≤
3.3 V
2.7 V
≤
V
DD
≤
3.3 V
V
DD
= 2.7 V; I
OH
= 2.9 mA
V
DD
= 2.7 V; I
OL
= 2.6 mA
Typical
2.0
0.8
2.2
0.4
Unit
V
V
V
V
Table 3. AC Characteristics (-40° C
≤
T
A
≤
85° C)
Symbol
t
PHL
t
PLH
t
r
t
f
Parameter
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
Output Rise Time
(10% to 90%)
Output Fall Time
(90% to 10%)
Condition*
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
LE
2.0
2.0
* See figure 5 for AC test circuit
Table 4. Typical Output Swing (V
DD
= 2.7 V)
Frequency
50 MHz
500 MHz
1500 MHz
Condition
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
Ω
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
Ω
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
Ω
Typical
2.3
2.3
2.2
Unit
Vp-p
Vp-p
Vp-p
O
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
BS
Document No. 70-0108-06
│
UltraCMOS™ RFIC Solutions
O
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Typical
4.1
3.9
Unit
ns
ns
ns
ns
PE3513
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
Latch-Up Avoidance
pin 1
NC
GND
IN
1
6
OUT
GND
V
DD
.
513
SC-70
2
5
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Description
Table 5. Pin Descriptions
Pin
No.
1
2
Pin
Name
N/C
GND
Device Functional Considerations
No Connect. This pin should be left open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Input signal pin. DC blocking capacitor
required (100 pF typical).
3
4
5
6
IN
V
DD
GND
OUT
Power supply pin. Bypassing is required.
Ground pin.
Table 6. Absolute Maximum Ratings
Symbol
V
DD
P
in
Parameter/Conditions
Supply voltage
Input Power
O
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
BS
13
T
ST
Storage temperature
range
-65
-40
150
85
T
OP
Operating temperature
range
ESD voltage (Human
Body Model)
V
ESD
2000
O
Min
Max
4.0
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
Document No. 70-0108-06
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LE
Units
V
dBm
°C
°C
V
The
PE3513
divides an input signal, up to a
frequency of 1500 MHz, by a factor of eight
thereby producing an output frequency at one-
eighth the input frequency. To work properly with
low impedance, ground referenced interfaces, the
input and output signals (pins 3 & 6) must be AC
coupled via an external capacitor, as shown in the
test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
TE
3
4
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
PE3513
Product Specification
Figure 4. Test Circuit Block Diagram
Spectrum
Analyzer
PE3513
2 GND
50 Ohm
100 pF
3 IN
GND 5
VDD 4
Signal
Generator
Figure 5. AC Test Circuit
BS
Pulse
Generator
R
T
Page 4 of 9
O
V
DD
PE3513
C
L
R
L
Document No. 70-0108-06
│
UltraCMOS™ RFIC Solutions
O
R
T =
Zout of pulse generator
(usually 50 ohm)
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
LE
VDD
3V +/- 0.15 V
TE
100 pF
100 pF
1000 pF
1 N/C
OUT 6
50 Ohm
PE3513
Product Specification
Typical Performance Data: V
DD
= 3.0 V
Figure 6. Input Sensitivity
Figure 7. Device Current
Figure 8. Output Power
O
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©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
BS
O
LE
TE
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