Ultra Low Power/High Speed CMOS SRAM
1M X 16 bit / 2M x 8-bit
Pb-Free and Green package materials are compliant to RoHS
BH616UV1611
n
FEATURES
Ÿ
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ÿ
Ultra low power consumption :
V
CC
= 3.6V
Operation current : 10mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 5.0uA (Typ.) at 3.0V/25
O
C
V
CC
= 1.2V
Data retention current : 1.5uA(Typ.) at 25
O
C
Ÿ
High speed access time :
-55
55ns (Max.) at V
CC
=1.65~3.6V
-70
70ns (Max.) at V
CC
=1.65~3.6V
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation, no clock, no refresh
Ÿ
Data retention supply voltage as low as 1.0V
n
DESCRIPTION
The BH616UV1611 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 1,048,576 by 16 bits
and operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.0V/25
O
C and maximum access time of 55ns at
1.65V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH616UV1611 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH616UV1611 is available in DICE form, JEDEC standard
48-pin TSOP-I and 48-ball BGA package.
n
POWER CONSUMPTION
POWER DISSIPATION
PRODUCT
FAMILY
BH616UV1611DI
BH616UV1611BI
BH616UV1611TI
Industrial
-40
O
C to +85
O
C
30uA
25uA
2mA
6mA
10mA
1.5mA
5mA
8mA
OPERATING
TEMPERATURE
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=1.8V
10MHz
f
Max.
V
CC
=3.6V
V
CC
=1.8V
1MHz
V
CC
=3.6V
10MHz
f
Max.
1MHz
DICE
BGA-48-0810
TSOP I-48
n
PIN CONFIGURATIONS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
A
B
C
D
E
F
G
H
LB
DQ8
DQ9
VSS
VCC
DQ14
DQ15
A18
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
5
A2
CE1
DQ1
DQ3
DQ4
DQ5
WE
A11
6
CE2
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
A16
BYTE
VSS
DQ15/A20
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE1
A0
n
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A19
A18
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 16384
BH616UV1611TI
16384
DQ0
.
.
.
.
.
.
DQ15
.
.
.
.
.
.
16
Data
Input
Buffer
Data
Output
Buffer
16
1024
Column Decoder
10
Control
Address Input Buffer
16
Column I/O
Write Driver
Sense Amp
16
2
OE
UB
DQ10
DQ11
DQ12
DQ13
A19
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
CE2, CE1
WE
OE
UB
LB
V
CC
V
SS
A16 A0 A17 A7 A6 A5 A4 A3 A2 A1
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV1611
1
Revision 1.3
Otc.
2006
BH616UV1611
n
PIN DESCRIPTIONS
Name
Function
A0 to A19 Address Input (word mode)
These 20 address inputs select one of the 1,024K x 16 bit in the RAM, if BYTE is HIGH
A0 to A20 Address Input (byte mode)
These 21 address inputs select one of the 2,048K x 8 bit in the RAM, If BYTE is LOW
(TSOP only)
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
CE1 Chip Enable 1 Input
data read from or write to the device. If either chip enable is not active, the device is
CE2 Chip Enable 2 Input
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
BYTE Byte Enable Input (TSOP only)
DQ0-DQ15 Data Input/Output
Ports
V
CC
V
SS
This input selects the organization of the SRAM. 1,024K x 16-bit configuration is
selected if BYTE is HIGH. 2,048K x 8-bit configuration is selected if BYTE is LOW
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
R0201-BH616UV1611
2
Revision 1.3
Otc.
2006
BH616UV1611
n
TRUTH TABLE
Byte Mode (TSOP only)
MODE
Chip
De-selected
(Power Down)
Output
Disabled
Read
(byte mode)
Write
(byte mode)
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
H
L
X
LB
X
X
X
X
X
UB
X
X
X
X
X
BYTE DQ0~DQ7 DQ8~DQ14 DQ15
L
L
L
L
L
High Z
High Z
High Z
D
OUT
D
IN
High Z
High Z
High Z
High Z
X
High Z
High Z
High Z
A20
A20
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
Word Mode
MODE
Chip
De-selected
(Power Down)
Output
Disabled
Read
(word mode)
CE1
H
X
X
L
CE2
X
L
X
H
WE
X
X
X
H
OE
X
X
X
H
LB
X
X
H
X
L
UB
X
X
H
X
L
L
H
L
L
H
BYTE DQ0~DQ7 DQ8~DQ14 DQ15
H
H
H
H
H
H
H
H
H
H
High Z
High Z
High Z
High Z
D
OUT
High Z
D
OUT
D
IN
X
D
IN
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
High Z
High Z
High Z
High Z
D
OUT
D
OUT
High Z
D
IN
D
IN
X
V
CC
CURRENT
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
L
H
H
L
H
L
L
Write
(word mode)
L
H
L
X
H
L
NOTES: H means V
IH
; L means V
IL
; X means don’t care (Must be V
IH
or V
IL
state)
48BGA ignore BYTE condition.
R0201-BH616UV1611
3
Revision 1.3
Otc.
2006
BH616UV1611
n
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
(1)
n
OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with
Respect to GND
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
RATING
-0.5
(2)
to 4.6V
-40 to +125
-60 to +150
1.0
20
RANG
Industrial
AMBIENT
TEMPERATURE
-40
O
C to + 85
O
C
V
CC
1.65V ~ 3.6V
C
C
O
n
CAPACITANCE
(1)
(T
A
= 25 C, f = 1.0MHz)
O
W
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
mA
C
IN
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2.
–2.0V
in case of AC pulse width less than 30 ns
C
IO
Input
Capacitance
Input/Output
Capacitance
V
IN
= 0V
V
I/O
= 0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
n
DC ELECTRICAL CHARACTERISTICS (T
A
= -40 C to +85 C)
PARAMETER
NAME
V
CC
V
IL
V
IH
I
IL
PARAMETER
Power Supply
V
CC
=1.8V
O
O
TEST CONDITIONS
MIN.
1.65
-0.3
(2)
1.4
2.2
--
TYP.
(1)
--
MAX.
3.6
0.4
0.8
UNITS
V
Input Low Voltage
V
CC
=3.6V
V
CC
=1.8V
--
V
Input High Voltage
V
CC
=3.6V
--
V
CC
+0.3
(3)
V
Input Leakage Current
V
IN
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
V
I/O
= 0V to V
CC
,
CE1 = V
IH
or CE2 = V
IL
or OE = V
IH
or
UB = LB = V
IH
V
CC
= Max, I
OL
= 0.2mA
V
CC
= Max, I
OL
= 2.0mA
V
CC
=1.8V
--
1
uA
I
LO
Output Leakage Current
--
--
1
0.2
0.4
uA
V
OL
V
OH
I
CC
I
CC1
I
CCSB
I
CCSB1
Output Low Voltage
--
V
CC
=3.6V
V
CC
=1.8V
V
CC
=3.6V
V
CC
=1.8V
--
V
Output High Voltage
Operating Power Supply
Current
Operating Power Supply
Current
Standby Current
–
TTL
V
CC
= Min, I
OH
= -0.1mA
V
CC
= Min, I
OH
= -1.0mA
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = F
MAX(4)
CE1 = V
IL
and CE2 = V
IH
,
I
DQ
= 0mA, f = 1MHz
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA
V
CC
-0.2
2.4
--
--
6
8
--
8
10
1.5
2.0
0.5
1.0
V
mA
V
CC
=3.6V
V
CC
=1.8V
--
V
CC
=3.6V
V
CC
=1.8V
1.0
1.5
mA
--
V
CC
=3.6V
V
CC
=1.8V
--
4.0
5.0
(5)
mA
Standby Current
–
CMOS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
--
V
CC
=3.6V
25
30
uA
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: V
CC
+1.0V in case of pulse width less than 20 ns.
4. F
MAX
=1/t
RC.
5. V
CC
=3.0V
R0201-BH616UV1611
4
Revision 1.3
Otc.
2006
BH616UV1611
n
DATA RETENTION CHARACTERISTICS (T
A
= -40 C to +85 C)
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
PARAMETER
V
CC
for Data Retention
O
O
TEST CONDITIONS
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
CE1≧V
CC
-0.2V or CE2≦0.2V,
V
IN
≧V
CC
-0.2V or V
IN
≦0.2V
V
CC
=1.2V
MIN.
1.0
TYP.
(1)
--
MAX.
--
UNITS
V
Data Retention Current
Chip Deselect to Data
Retention Time
--
1.5
15
uA
0
See Retention Waveform
t
RC (2)
--
--
ns
Operation Recovery Time
--
--
ns
1. Typical characteristics are at T
A
=25
O
C and not 100% tested.
2. t
RC
= Read Cycle Time.
n
LOW V
CC
DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
CC
V
IH
V
CC
V
DR
≧1.0V
V
CC
t
CDR
CE1≧V
CC
- 0.2V
t
R
V
IH
CE1
n
LOW V
CC
DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
CC
V
DR
≧1.0V
V
CC
V
CC
t
CDR
t
R
CE2≦0.2V
CE2
V
IL
V
IL
n
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Level
t
CLZ1
, t
CLZ2
, t
BE
, t
OLZ
, t
CHZ1
,
t
CHZ2
, t
BDO
, t
OHZ
, t
WHZ
, t
OW
Output Load
Others
V
CC
/ 0V
1V/ns
0.5Vcc
C
L
= 5pF+1TTL
C
L
= 30pF+1TTL
ALL INPUT PULSES
1 TTL
Output
C
L(1)
V
CC
GND
10%
90%
90%
10%
n
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM
“H”
TO
“L”
MAY CHANGE
FROM
“L”
TO
“H”
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE CHANGE
FROM
“H”
TO
“L”
WILL BE CHANGE
FROM
“L”
TO
“H”
CHANGE :
STATE UNKNOW
CENTER LINE IS
HIGH INPEDANCE
“OFF”
STATE
→ ←
Rise Time:
1V/ns
→ ←
Fall Time:
1V/ns
1. Including jig and scope capacitance.
R0201-BH616UV1611
5
Revision 1.3
Otc.
2006
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