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9763-11

Description
1.85mm Male to SSMA Male Adapter
CategoryAnalog mixed-signal IC    The signal circuit   
File Size287KB,15 Pages
ManufacturerpSemi (peregrine semiconductor)
Websitehttp://www.psemi.com/
Download Datasheet Parametric Compare View All

9763-11 Overview

1.85mm Male to SSMA Male Adapter

9763-11 Parametric

Parameter NameAttribute value
MakerpSemi (peregrine semiconductor)
Parts packaging codeQFJ
package instructionQCCJ, LDCC68,1.0SQ
Contacts68
Reach Compliance Codecompli
Is SamacsysN
Analog Integrated Circuits - Other TypesPLL FREQUENCY SYNTHESIZER
JESD-30 codeS-CQCC-J68
Number of terminals68
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
power supply3 V
Certification statusNot Qualified
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Base Number Matches1
Product Specification
PE9763
Product Description
Peregrine’s PE9763 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.2 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE9763 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, a phase comparator and a
charge pump as shown in Figure 1. Counter values are
programmable through either a serial interface or directly hard-
wired.
PE9763 is optimized for commercial space applications. Single
Event Latch up (SEL) is physically impossible and Single Event
Upset (SEU) is better than 10-9 errors per bit / day. Fabricated
in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS
technology, the PE9763 offers excellent RF performance and
intrinsic radiation tolerance.
3.2 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Features
3.2 GHz operation
÷10/11 dual modulus prescaler
Selectable phase detector or charge
pump output
Serial or Direct mode access
Frequency selectivity: Comparison
frequency / 2
18
Low power —- 25 - 30 mA at 3V (phase
detector / charge pump)
Rad-Hard
Ultra-low phase noise
68-lead CQFJ or Die
Figure 1. Block Diagram
F
in
F
in
M
8:0
A
3:0
R
5:0
Pre_en
Sdata
Primary
21-bit
Latch
Prescaler
10/11
Main
Counter
13
PD_U
20
Secon-
dary
20-bit
Latch
Auxilia-
ry
20-bit
Latch
+
13
20
18
DSM
19
4
6
6
Phase
Detector
PD_D
Charge
Pump
CP
f
r
18
K
17:0
Direct
2
R Counter
Document No. 70-0140-01
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15

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