Product Specification
PE9763
Product Description
Peregrine’s PE9763 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.2 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE9763 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, a phase comparator and a
charge pump as shown in Figure 1. Counter values are
programmable through either a serial interface or directly hard-
wired.
PE9763 is optimized for commercial space applications. Single
Event Latch up (SEL) is physically impossible and Single Event
Upset (SEU) is better than 10-9 errors per bit / day. Fabricated
in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS
technology, the PE9763 offers excellent RF performance and
intrinsic radiation tolerance.
3.2 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Features
•
3.2 GHz operation
•
÷10/11 dual modulus prescaler
•
Selectable phase detector or charge
pump output
•
Serial or Direct mode access
•
Frequency selectivity: Comparison
frequency / 2
18
•
Low power —- 25 - 30 mA at 3V (phase
detector / charge pump)
•
Rad-Hard
•
Ultra-low phase noise
•
68-lead CQFJ or Die
Figure 1. Block Diagram
F
in
F
in
M
8:0
A
3:0
R
5:0
Pre_en
Sdata
Primary
21-bit
Latch
Prescaler
10/11
Main
Counter
13
PD_U
20
Secon-
dary
20-bit
Latch
Auxilia-
ry
20-bit
Latch
+
13
20
18
DSM
19
4
6
6
Phase
Detector
PD_D
Charge
Pump
CP
f
r
18
K
17:0
Direct
2
R Counter
Document No. 70-0140-01
│
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE9763
Product Specification
Figure 2. Pin Configuration
RAND_EN
MS2_SEL
CPSEL
GND
GND
61
ENH
V
DD
V
DD
63
F
R
62
R
5
R
4
R
3
R
2
R
1
R
0
K
1
K
0
68
67
65
66
64
9
7
6
4
2
8
5
3
1
V
DD
10
K
2
11
K
3
12
K
4
13
K
5
14
K
6
15
K
7
16
K
8
17
K
9
18
K
10
19
K
11
20
K
12
21
K
13
22
K
14
23
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
V
DD
28
GND
29
M
0
30
M
1
31
M
2
32
M
3
33
M
4
34
M
5
35
M
6
36
M
7
37
M
8
38
A
0
39
A
1
40
A
2
41
A
3
42
DIRECT
43
PRE_EN
V
DD
V
DD
GND
PD_U
CP
PD_D
GND
V
DD
D
OUT
LD
C
EXT
GND
FIN
FIN
V
DD
GND
V
DD
K
15
24
K
16
25
K
17
26
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
GND
V
DD
10
V
DD
11
12
13
14
15
K
2
K
3
K
4
K
5
K
6
Direct
Direct
Direct
Direct
Direct
(Note 1)
Input
Input
Input
Input
Input
Digital core V
DD
.
K Counter bit2.
K Counter bit3.
K Counter bit4.
K Counter bit5.
K Counter bit6.
Document No. 70-0140-01
│
UltraCMOS™ RFIC Solutions
Downbond
(Note 1)
ESD ground.
ESD V
DD
.
Pin
Name
R
0
R
1
R
2
R
3
R
4
R
5
K
0
K
1
GND
Valid
Mode
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Type
Input
Input
Input
Input
Input
Input
Input
Input
Downbond
R Counter bit0 (LSB).
R Counter bit1.
R Counter bit2.
R Counter bit3.
R Counter bit4.
R Counter bit5 (MSB).
K Counter bit0 (LSB).
K Counter bit1.
Digital core ground.
Description
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
PE9763
Product Specification
Pin No.
16
17
18
19
20
21
22
23
24
25
26
27
Pin
Name
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
K
15
K
16
K
17
V
DD
V
DD
GND
Valid
Mode
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Direct
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
(Note 1)
Downbond
Downbond
K Counter bit7.
K Counter bit8.
K Counter bit9.
K Counter bit10.
K Counter bit11.
K Counter bit12.
K Counter bit13.
K Counter bit14.
K Counter bit15.
K Counter bit16.
K Counter bit17 (MSB).
Digital core V
DD
.
ESD V
DD
.
Digital core ground.
ESD ground.
M Counter bit0 (LSB).
M Counter bit1.
M Counter bit2
M Counter bit3.
M Counter bit4.
Description
28
GND
29
30
31
32
M
0
M
1
M
2
M
3
M
4
33
S_WR
M
5
34
SDATA
M
6
35
SCLK
36
37
38
M
7
M
8
A
0
A
1
39
E_WR
40
41
42
43
44
45
GND
Downbond
ESD ground.
A
2
A
3
DIRECT
Pre_en
V
DD
GND
Direct
Direct
Direct
Direct
Direct
Serial
Direct
Serial
Direct
Serial
Direct
Direct
Direct
Direct
Serial
Direct
Direct
Both
Direct
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Downbond
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register
data are transferred to the secondary register on S_WR or Hop_WR rising edge.
M Counter bit5.
Binary serial data input. Input data entered MSB first.
M Counter bit6.
Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
M Counter bit7.
M Counter bit8 (MSB).
A Counter bit0 (LSB).
A Counter bit1.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
A Counter bit2.
A Counter bit3 (MSB).
Direct mode select. “High” enables direct mode. “Low” enables serial mode.
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Digital core V
DD
.
Digital core ground.
Document No. 70-0140-01
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
PE9763
Product Specification
Pin No.
Pin
Name
V
DD
Valid
Mode
Type
(Note 1)
(Note 1)
ESD V
DD
.
Prescaler V
DD
.
Description
46
V
DD
47
48
F
in
F
in
Both
GND
49
GND
GND
50
CEXT
Downbond
Downbond
Downbond
Output
Both
Input
Input
Prescaler input from the VCO. 3.2 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 W resistor directly to the ground plane.
Prescaler ground.
Prescaler ground.
Output driver/charge pump ground.
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kW series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier
used for driving LD.
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Data out function, enabled in enhancement mode.
Output driver/charge pump V
DD
.
Output driver/charge pump ground.
PD_D pulses down when f
p
leads f
c
. PD_U is driven to GND when CPSEL = “High”.
Charge pump output. Selected when CPSEL = “1”. Tristate when CPSEL = “Low”.
PD_U pulses down when f
c
leads f
p
. PD_D is driven to GND when CPSEL = “High”.
Output driver/charge pump ground.
Output driver/charge pump V
DD
.
Phase detector GND.
Phase detector V
DD
.
ESD V
DD
.
ESD ground.
Reference ground.
Reference frequency input.
Reference V
DD
.
Digital core V
DD
.
Digital core ground.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
Charge pump select. “High” enables the charge pump and disables pins PD_U and PD_D by
forcing them “low”. A “low” Tri-states the CP and enables PD_U and PD_D.
MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit
is the phase detector comparison frequency / 2
19
.
Both
Both
Both
51
52
53
54
55
56
57
58
59
LD
D
OUT
V
DD
GND
PD_D
CP
PD_U
GND
V
DD
GND
V
DD
Output
Output
(Note 1)
Downbond
Both
Both
Both
Output
Output
Output
Downbond
(Note 1)
Downbond
(Note 1)
(Note 1)
Downbond
Downbond
60
V
DD
GND
61
GND
62
63
64
f
r
V
DD
V
DD
GND
65
66
67
68
Note 1:
Note 2:
ENH
CPSEL
MS2_SEL
RND_SEL
Both
Both
Both
Both
Input
(Note 1)
(Note 1)
Downbond
Input
Input
Input
Input
Both
All V
DD
pins are connected by diodes and must be supplied with the same positive voltage level.
All digital input pins have 70 kΩ pull-down resistors to ground.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0140-01
│
UltraCMOS™ RFIC Solutions
PE9763
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Electrostatic Discharge (ESD) Precautions
Units
V
V
mA
mA
°C
4.0
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature range
Min
-0.3
-0.3
-10
-10
-65
Max
V
DD
+
0.3
+10
+10
150
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Table 3. Operating Ratings
Symbol
V
DD
T
A
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Min
2.85
-40
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Max
3.15
85
Units
V
°C
Table 4. ESD Ratings
Symbol
V
ESD
Note 1:
Parameter/Conditions
ESD voltage human body model
(Note 1)
Level
1000
Units
V
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Document No. 70-0140-01
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15
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