NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
D
P48N02LD
TO-252 (D PAK)
PRODUCT SUMMARY
V
(BR)DSS
25
R
DS(ON)
14mΩ
I
D
52A
G
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (T
C
= 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy
Power Dissipation
2
1
SYMBOL
V
GS
LIMITS
±20
52
35
156
33
250
8.6
45
25
-55 to 150
275
UNITS
V
T
C
= 25 °C
T
C
= 100 °C
I
D
I
DM
I
AR
A
L = 0.1mH
L = 0.05mH
T
C
= 25 °C
T
C
= 100 °C
E
AS
E
AR
P
D
T
j
, T
stg
T
L
mJ
W
Operating Junction & Storage Temperature Range
Lead Temperature ( /
16
” from case for 10 sec.)
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
Junction-to-Ambient
Case-to-Heatsink
1
2
1
°C
SYMBOL
R
θJC
R
θJA
R
θCS
TYPICAL
MAXIMUM
2.5
65
UNITS
°C / W
0.7
Pulse width limited by maximum junction temperature.
Duty cycle
≤
1％
ELECTRICAL CHARACTERISTICS (T
C
= 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
V
GS
= 0V, I
D
= 250µA
V
DS
= V
GS
, I
D
= 250µA
V
DS
= 0V, V
GS
= ±20V
V
DS
= 20V, V
GS
= 0V
V
DS
= 20V, V
GS
= 0V, T
C
= 125 °C
25
1
1.6
3
±250
25
250
nA
µA
V
LIMITS
UNIT
MIN TYP MAX
1
JUL-11-2001
NIKO-SEM
1
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
I
D(ON)
R
DS(ON)
1
P48N02LD
TO-252 (D PAK)
On-State Drain Current
Drain-Source On-State
1
Resistance
V
DS
= 10V, V
GS
= 10V
V
GS
= 4.5V, I
D
= 21A
V
GS
= 10V, I
D
= 26A
V
DS
= 10V, I
D
= 26A
DYNAMIC
60
16
11
32
20
14
A
mΩ
S
Forward Transconductance
g
fs
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
2
2
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
2
1200 1800
V
GS
= 0V, V
DS
= 15V, f = 1MHz
600
350
35
V
DS
= 10V, V
GS
= 10V,
I
D
= 52A
8
5
6
V
DS
= 15V, R
L
= 1Ω
I
D
≅
52A, V
GS
= 10V, R
GEN
= 24Ω
120
40
105
16
250
90
200
nS
1000
500
60
nC
pF
Gate-Source Charge
Gate-Drain Charge
2
2
Turn-On Delay Time
Rise Time
t
d(on)
t
r
Turn-Off Delay Time
Fall Time
2
2
t
d(off)
t
f
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T
C
= 25 °C)
Continuous Current
Pulsed Current
3
1
I
S
I
SM
V
SD
t
rr
I
RM(REC)
Q
rr
I
F
= I
S
, dl
F
/dt = 100A /
µS
I
S
= 26A, V
GS
= 0V
0.9
70
200
0.043
52
156
1.3
A
V
nS
A
µC
Forward Voltage
Reverse Recovery Time
Peak Reverse Recovery Current
Reverse Recovery Charge
1
2
Pulse test : Pulse Width
≤
300
µsec,
Duty Cycle
≤
2％.
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
REMARK: THE PRODUCT MARKED WITH “P48N02LD”, DATE CODE or LOT #
2
JUL-11-2001
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P48N02LD
TO-252 (D PAK)
TO-252 (DPAK) MECHANICAL DATA
mm
Dimension
Min.
A
B
C
D
E
F
G
9.35
2.2
0.48
0.89
0.45
0.03
6
Typ.
Max.
10.1
2.4
0.6
1.5
0.6
0.23
6.2
H
I
J
K
L
M
N
6.4
5.2
0.6
0.64
4.4
Dimension
Min.
Typ.
0.8
6.6
5.4
1
0.9
4.6
Max.
mm
3
JUL-11-2001
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
