Z8 Encore!
®
Motor Control Series
Z8 Encore!
®
Z8FMC16 MCU
Programming Specification
PRS000502-1005
PRELIMINARY
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PRS000502-1005
PRELIMINARY
Z8FMC16 MCU
Programming Specification
1
Flash Memory Programming Overview
The Z8 Encore!
®
Z8FMC16 Motor Control features a Flash program memory selections
of 8KB or 16KB. By using Flash memory, you have the ability to easily update the code.
The Z8 Encore!
®
features an on-chip Flash controller that typically manages the timing of
Flash control signals for programming, page erase, and mass erase operations. The Flash
controller can also be bypassed to allow direct control of Flash signals via the general
purpose input/output (GPIO) pins. Flash memory can be programmed faster by controlling
the Flash memory signals directly. Bypassing the Flash controller is beneficial when
programming a large number of devices, and is most likely to be used by third party
vendors who are developing the multi-site gang programmers.
Bypassing the Flash Controller
Flash controller bypass mode is enabled by writing the following three bytes of instruction
to the on-chip debugger (OCD) via the DBG interface:
1.
80H
- This instruction initiates auto-baud calculation of the DBG interface data and
clock rate.
2.
F0H
- OCD writes testmode register command.
3.
04H
- Data to be written to the testmode register. This data enables the Flash
controller bypass mode.
Flash Memory Control Signals
Depending on the size (number of bytes) available in the Flash memory, the Flash memory
uses fourty two signals for its direct interfacing.
•
•
•
•
16 signals for the address lines.
8 signals for data input.
8 signals for data output.
10 signals for control operations.
The Flash memory control signals are listed and described in
Table 1
PRS000502-1005
PRELIMINARY
Flash Memory Programming Overview
Z8FMC16 MCU
Programming Specification
2
.
Table 1. Flash Memory Control Signals
Signal
Direction
I
Description
XADDR[9:0]
X address input selects a row. XADDR[9:0] corresponds to the upper
10 bits of the program memory address space (PROGMEM[15:6]).
For Z8 Encore!
®
devices with less than 64KB of program memory, the
unused upper address bits must be set to 0.
Y address input selects one byte within a row. YADDR[5:0]
corresponds to the lower 6 bits of the program memory address space
(PROGMEM[5:0]).
Data input.
Data output.
X address enable.
Y address enable.
Sense amplifier enable.
Output enable.
Erase enable. This signal is used to select erase operations.
Mass erase select. This signal is used to distinguish between page
erase and mass erase operations.
Program enable. This signal is used to select a program operation.
Non-volatile store enable. This signal is used during page erase, mass
erase, and programming operations.
This signal should be set to 1 during all operations.
Information area select.
YADDR[5:0]
I
DIN[7:0]
DOUT[7:0]
XE
YE
SE
OE
ERASE
MAS1
PROG
NVSTR
TMR
IFREN
I
O
I
I
I
I
I
I
I
I
I
I
Flash Memory Operations
When bypassing the Flash controller, all Flash memory operations (read, program, page
erase, and mass erase) are available. The mode of operation is set by the Flash memory
control signals as described in
Table 2.
The selection of the Flash main memory or the Flash information area depends on the
IFREN signal as described in
Table 3.
PRS000502-1005
PRELIMINARY
Flash Memory Programming Overview
Z8FMC16 MCU
Programming Specification
3
Table 2. Flash Mode Truth Table
Mode
XE
YE
SE
OE
PROG
ERASE MAS1
NVSTR TMR
IFREN
Read
Program
Page Erase
Mass Erase
H
H
H
H
H
H
L
L
H
L
L
L
H
L
L
L
L
H
L
L
L
L
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L/H
1
L/H
1
L/H
1
L/H
1
See
Table 3
for IFREN signal operation information.
Table 3. IFREN Signal Truth Table
Mode
IFREN = 1
IFREN = 0
Read
Program
Page Erase
Mass Erase
Read Information Area
Page Erase Information
Area
Mass Erase Information
Area
Read Main Memory
Page Erase Main Memory
Mass Erase Main Memory
Program Information Area Program Main Memory
Flash Bypass Mode Register Structure
For using Flash controller bypass mode for all package sizes, the signals must be
registered internally. This allows all data access to occur through pin PWM2L and Port A
[6:0]. Three other pins (PWM2H, PWM1L, and PWM1H), selects one of the input data
registers or the data output register as shown in
Table 4.
PRS000502-1005
PRELIMINARY
Flash Memory Programming Overview
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