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ATV2500H-35KC

Description
High-Density UV-Erasable Programmable Logic Device
CategoryProgrammable logic devices    Programmable logic   
File Size458KB,15 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

ATV2500H-35KC Overview

High-Density UV-Erasable Programmable Logic Device

ATV2500H-35KC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAtmel (Microchip)
Parts packaging codeLCC
package instructionWQCCJ, LDCC44,.7SQ
Contacts44
Reach Compliance Codeunknow
Other features24 MACROCELLS
maximum clock frequency28 MHz
In-system programmableNO
JESD-30 codeS-CQCC-J44
JESD-609 codee0
JTAG BSTNO
length16.5862 mm
Humidity sensitivity level2
Dedicated input times14
Number of I/O lines24
Number of macro cells24
Number of terminals44
Maximum operating temperature70 °C
Minimum operating temperature
organize14 DEDICATED INPUTS, 24 I/O
Output functionMACROCELL
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeWQCCJ
Encapsulate equivalent codeLDCC44,.7SQ
Package shapeSQUARE
Package formCHIP CARRIER, WINDOW
Peak Reflow Temperature (Celsius)225
power supply5 V
Programmable logic typeUV PLD
propagation delay35 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width16.5862 mm
Features
Third Generation Programmable Logic Structure
– Easily Achieves Gate Utilization Factors of 80 Percent
Increased Logic Flexibility
– 86 Inputs and 72 Sum Terms
Flexible Output Macrocell
– 48 Flip-Flops - 2 per Macrocell
– 3 Sum Terms - Can Be OR'ed and Shared
High-Speed
Low-Power — Less than 0.5 mA Typical (ATV2500L)
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Asynchronous Clocks and Resets
– Multiple Synchronous Presets - One per Four or Eight Flip-Flops
Proven and Reliable High Speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
Reprogrammable - Tested 100% for Programmability
40-pin Dual-In-line and 44-Lead Surface Mount Packages
High-Density
UV-Erasable
Programmable
Logic Device
ATV2500H
ATV2500L
Block Diagram
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40-
pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
(continued)
Pin Configurations
Pin Name
IN
I/O
I/O, 0,2,4..
I/O, 1,3,5..
*
VCC
Function
Logic Inputs
Bidirectional Buffers
“Even” I/O Buffers
“Odd” I/O Buffers
No Internal Connection
+5V Supply
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC/LCC
I/O1
I/O0
*
IN
IN
IN
IN
IN
IN
IN
I/O06
* = No Connect
Rev. 0025E–05/98
I/O12
IN
IN
IN
IN
IN
IN
IN
*
I/O18
I/O19
18
19
20
21
22
23
24
25
26
27
28
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
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