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ATA555812-PP

Description
1 kbit R/W IDIC with Deterministic Anticollision
File Size546KB,42 Pages
ManufacturerAtmel (Microchip)
Download Datasheet View All

ATA555812-PP Overview

1 kbit R/W IDIC with Deterministic Anticollision

Features
Contactless Read/Write Data Transmission
Radio Frequency f
RF
:
100 kHz to 200 kHz
User Memory (1024 Bits): 32 Write Protectable 32-bit Blocks of Data
Deterministic Anticollision: Detection Rate ~ 20 Tags/s with 40-bit Tag ID, RF/32
On-chip CRC Generator: 16-bit CRC-CCITT Compliant to ISO/IEC 11785
Downlink Transmission:
Enhanced
1 out of 4
Pulse Interval Encoding (~ 5 kbps)
Uplink Transmission:
ASK Modulated, NRZ, Manchester or Bi-phase Encoding
Integrated Tuning Capacitor: 75 pF ±10% as Mask Option
System Memory (320 bits):
– 10 Write and Password Protectable 32 Bit Blocks of Data
– Tag ID (96 Bits Maximum)
– Traceability Data with Inherent Manufacturer Serial Number
– Write Password (32 Bits) and Read Password (32 Bits),
with Page Orientated Memory Protection Areas
– Configuration Register for Setup of:
• Selectable Data Bit Rate: RF/2 .. RF/64
• Selectable Tag ID Length to Optimize Anticollision Detection Rate
• Start of Frame with Variable Preamble Length to Simplify Interrogator Design
• Public Mode (PM) for Read Only Tag Emulation
• Electrical Article Surveillance (EAS) Mode
• Direct Data (NRZ), Bi-phase (FDX-B) or Manchester Data Encoding
1 kbit R/W IDIC
®
with
Deterministic
Anticollision
ATA5558
Preliminary
1. General Description
The ATA5558 is a contactless, two-terminal R/W-Identification IC (IDIC
®
) for multi- or
single tag applications in the low frequency (≈ 125 kHz) range. The passive tag uses
the external RF signal to generate it’s own power supply and internal clock reference.
Figure 1-1.
RFID System Using an ATA5558 Tag
Transponder
Coil interface
Power
Reader or
Base station
Interrogator
Data
Controller
*
Memory
ATA5558
* Mask option
It contains an EEPROM which is subdivided into 1024 bits of user memory and
320 bits of system memory. Both memory sections are organized in data blocks of
32 bits, each equipped with an associated lock bit for block write protection. The user
memory, which is intended for storage of recallable user data, is made of 32 such
blocks. The 10 block system memory section is reserved for system parameter and
configuration settings. Two of these blocks include a 32 bit read and a 32 bit write
password to prevent unauthorized read and/or write access to protected user defin-
able memory pages.
Rev. 4681C–RFID–09/05
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