Features
•
80C52 Compatible
– Four 8-bit I/O Ports
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 8 Interrupt Sources with 4 Priority Levels
– Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
High-speed Architecture
– 10 to 40 MHz in Standard Mode
16K/32K Bytes On-Chip ROM Program
T80C51RD2 ROMless Versions
On-Chip 1024 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024 bytes)
– 256 Bytes Selected at Reset for AT87C51RB2/RC2 Compatibility
Keyboard Interrupt Interface on Port P1
8-bit Clock Prescaler
64K Program and Data Memory Spaces
Improved X2 Mode with Independant Selection for CPU and Each Peripheral
Programmable Counter Array 5 Channels with:
– High-speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Full Duplex Enhanced UART
Dedicated Baud Rate Generator for UART
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-out)
Power Control Modes
– Idle Mode
– Power-down Mode
– Power-off Flag
Power Supply: 2.7V to 5.5V or 2.7V to 3.6V
Temperature Ranges: Commercial (0 to +70°C) and Industrial (-40°C to +85°C)
Packages: PDIL40, PLCC44, VQFP44
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80C51 High
Performance
ROM 8-bit
Microcontroller
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AT80C51RD2
AT83C51RB2
AT83C51RC2
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Description
AT8xC51Rx2 microcontrollers are high performance ROM versions of the 80C51 8-bit
microcontrollers. They contain a 0K, 16K or 32K bytes ROM memory block for
program.
The microcontrollers retain all features of the Atmel 80C52 with 256 bytes of internal
RAM, a 7-source 4-level interrupt controller and three timer/counters.
In addition, the microcontrollers have a Programmable Counter Array, an XRAM of
1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a more versatile serial
channel that facilitates multiprocessor communication (EUART) and a speed improve-
ment mechanism (X2 mode).
The microcontrollers have 2 software-selectable modes of reduced activity and 8 bit
clock prescaler for further reduction in power consumption. In Idle mode, the CPU is
frozen while the peripherals and the interrupt system are still operating. In the Power-
down mode, the RAM is saved and all other functions are inoperative.
Rev. 4113B–8051–03/05
Table 1.
Memory Size
ROM (Bytes)
AT83C51RB2
AT83C51RC2
AT80C51RD2
16K
32K
ROMless
XRAM (Bytes)
1024
1024
1024
TOTAL RAM
(Bytes)
1280
1280
1280
I/O
32
32
32
Block Diagram
T2EX
RxD
TxD
VCC
Vss
PCA
ECI
T2
(1)
Key
Board
(2) (2)
XTAL1
XTAL2
(1)
(1) (1)
EUART
+
BRG
RAM
256x8
ROM
32Kx8 or
16Kx8
XRAM
1Kx8
PCA
Timer2
ALE/ PROG
PSEN
CPU
EA
RD
WR
(2)
(2)
C51
CORE
IB-bus
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3
Watch
Dog
(2) (2)
RESET
T0
T1
(2) (2)
P1
P2
INT0
INT1
P0
P3
Notes:
1. Alternate function of Port 1
2. Alternate function of Port 3
2
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Pin Configurations
P1.0/T2
P1.1/T2EX
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.7CEX4
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
ALE/PROG
PSEN
P2.7/AD15
P2.6/AD14
P2.5/AD13
P2.4/AD12
P2.3/AD11
P2.2/AD10
P2.1/AD9
P2.0/AD8
P1.5/CEX2
P1.6/CEX3
P1.7/CEx4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
P1.4/CEX1
P1.3/CEX0
P1.1/T2EX
PDIL40
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
PLCC44
18 19 20 21 22 23 24 25 26 27 28
P1.4/CEX1
P1.3/CEX0
P1.1/T2EX
P3.6/WR
P2.2/A10
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
VQFP44 1.4
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11
P2.4/A12
XTAL1
P3.6/WR
P3.7/RD
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
XTAL2
VSS
*NIC: No Internal Connection
P0.3/AD3
P1.2/ECI
P1.0/T2
NIC*
VCC
P2.3/A11
P2.4/A12
P3.7/RD
NIC*
P2.0/A8
P2.1/A9
XTAL2
XTAL1
VSS
P0.2/AD2
P0.3/AD3
P0.0/AD0
P0.1/AD1
P1.2/ECI
P1.0/T2
VCC
NIC*
3
4113B–8051–03/05
Table 2.
Pin Description
Pin Number
Mnemonic
V
SS
V
CC
P0.0 - P0.7
DIL
20
40
39 - 32
PLCC44
22
44
43 - 36
VQFP44 1.4
16
38
37 - 30
Type
I
I
I/O
Name and Function
Ground:
0V reference
Power Supply:
This is the power supply voltage for normal, idle and power-down
operation
Port 0:
Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 must be
polarized to V
CC
or V
SS
in order to prevent any parasitic current consumption. Port
0 is also the multiplexed low-order address and data bus during access to external
program and data memory. In this application, it uses strong internal pull-up when
emitting 1s. Port 0 also inputs the code bytes during EPROM programming.
External pull-ups are required during program verification during which P0 outputs
the code bytes.
Port 1:
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 1 pins that are externally pulled low will source
current because of the internal pull-ups. Port 1 also receives the low-order address
byte during memory programming and verification.
Alternate functions for T89C51RB2/RC2 Port 1 include:
1
2
40
I/O
I/O
2
3
41
I/O
I
3
4
42
I/O
I
4
5
43
I/O
I/O
5
6
44
I/O
I/O
6
7
1
I/O
I/O
7
8
2
I/O
I/O
8
9
3
I/O
I/O
XTAL1
XTAL2
19
18
21
20
15
14
I
O
P1.0:
Input/Output
T2 (P1.0):
Timer/Counter 2 external count input/Clockout
P1.1:
Input/Output
T2EX:
Timer/Counter 2 Reload/Capture/Direction Control
P1.2:
Input/Output
ECI:
External Clock for the PCA
P1.3:
Input/Output
CEX0:
Capture/Compare External I/O for PCA module 0
P1.4:
Input/Output
CEX1:
Capture/Compare External I/O for PCA module 1
P1.5:
Input/Output
CEX2:
Capture/Compare External I/O for PCA module 2
P1.6:
Input/Output
CEX3:
Capture/Compare External I/O for PCA module 3
P1.7:
Input/Output:
CEX4:
Capture/Compare External I/O for PCA module 4
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier
P1.0 - P1.7
1-8
2-9
40 - 44
1-3
I/O
4
AT80C51RD2/AT83C51Rx2
4113B–8051–03/05
AT80C51RD2/AT83C51Rx2
Table 2.
Pin Description (Continued)
Pin Number
Mnemonic
P2.0 - P2.7
DIL
21 - 28
PLCC44
24 - 31
VQFP44 1.4
18 - 25
Type
I/O
Name and Function
Port 2:
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 2 pins that are externally pulled low will source
current because of the internal pull-ups. Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during ROM reading and
verification:
P2.0 to P2.5 for 16 KB devices
P2.0 to P2.6 for 32 KB devices
P3.0 - P3.7
10 - 17
11,
13 - 19
5,
7 - 13
I/O
Port 3:
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and can be
used as inputs. As inputs, Port 3 pins that are externally pulled low will source
current because of the internal pull-ups. Port 3 also serves the special features of
the 80C51 family, as listed below.
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
INT1 (P3.3):
External interrupt 1
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V
SS
permits a power-on reset
using only an external capacitor to V
CC
. This pin is an output when the hardware
watchdog forces a system reset.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of
the address during an access to external memory. In normal operation, ALE is
emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can
be used for external timing or clocking. Note that one ALE pulse is skipped during
each access to external data memory. This pin is also the program pulse input
(PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0
bit. With this bit set, ALE will be inactive during internal fetches.
Program Strobe Enable:
The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable:
EA must be externally held low to enable the device to
fetch code from external program memory locations 0000H to 3FFFH (16K),
7FFFH (32K). If security level 1 is programmed, EA will be internally latched on
Reset.
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
RST
9
10
4
I/O
ALE/PROG
30
33
27
O (I)
PSEN
29
32
26
O
EA
31
35
29
I
5
4113B–8051–03/05
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