AT29C010A-12PI datasheet, PDF - EEWORLD Datasheet

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AT29C010A-12PI: Description128K X 8 FLASH 5V PROM, 90 ns, PDSO32; Categorystorage storage; File Size207KB，18 Pages; ManufacturerAtmel (Microchip)

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AT29C010A-12PI Overview

128K X 8 FLASH 5V PROM, 90 ns, PDSO32

AT29C010A-12PI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	0.600 INCH, PLASTIC, DIP-32
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	120 ns
startup block	BOTTOM/TOP
command user interface	NO
Data polling	YES
JESD-30 code	R-PDIP-T32
JESD-609 code	e0
length	42.037 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	1,1,1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP32,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	4.826 mm
Department size	8K,112K,8K
Maximum standby current	0.0003 A
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
switch bit	YES
type	NOR TYPE
width	15.24 mm
Maximum write cycle time (tWC)	10 ms
Base Number Matches	1

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Features

•

Fast Read Access Time – 70 ns

•

5-volt Only Reprogramming

•

Sector Program Operation

– Single Cycle Reprogram (Erase and Program)

– 1024 Sectors (128 Bytes/sector)

– Internal Address and Data Latches for 128 Bytes

Two 8K Bytes Boot Blocks with Lockout

Internal Program Control and Timer

Hardware and Software Data Protection

Fast Sector Program Cycle Time – 10 ms

DATA Polling for End of Program Detection

Low Power Dissipation

– 50 mA Active Current

– 100 µA CMOS Standby Current

Typical Endurance > 10,000 Cycles

Single 5V

10% Supply

CMOS and TTL Compatible Inputs and Outputs

Commercial and Industrial Temperature Ranges

•

1-Megabit

(128K x 8)

5-volt Only

Flash Memory

AT29C010A

Description

The AT29C010A is a 5-volt-only in-system Flash programmable and erasable read

only memory (PEROM). Its 1 megabit of memory is organized as 131,072 words by

8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device

offers access times to 70 ns with power dissipation of just 275 mW over the commer-

cial temperature range. When the device is deselected, the CMOS standby current is

Pin Configurations

Pin Name

A0 - A16

I/O0 - I/O7

Function

Addresses

Chip Enable

Output Enable

Write Enable

Data Inputs/Outputs

No Connect

DIP Top View

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

TSOP Top View

Type 1

A11

A13

A14

VCC

A16

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

PLCC Top View

A12

A15

A16

VCC

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

I/O0

A14

A13

A11

A10

I/O7

Rev. 0394E–FLASH–11/02

less than 100 µA. The device endurance is such that any sector can typically be written

to in excess of 10,000 times.

To allow for simple in-system reprogrammability, the AT29C010A does not require high

input voltages for programming. Five-volt-only commands determine the operation of

the device. Reading data out of the device is similar to reading from an EPROM. Repro-

gramming the AT29C010A is performed on a sector basis; 128 bytes of data are loaded

into the device and then simultaneously programmed.

During a reprogram cycle, the address locations and 128 bytes of data are internally

latched, freeing the address and data bus for other operations. Following the initiation of

a program cycle, the device will automatically erase the sector and then program the

latched data using an internal control timer. The end of a program cycle can be detected

by DATA polling of I/O7. Once the end of a program cycle has been detected, a new

access for a read or program can begin.

Block Diagram

Device Operation

READ:

The AT29C010A is accessed like an EPROM. When CE and OE are low and

WE is high, the data stored at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high impedance state whenever CE

or OE is high. This dual-line control gives designers flexibility in preventing bus

contention.

BYTE LOAD:

Byte loads are used to enter the 128 bytes of a sector to be programmed

or the software codes for data protection. A byte load is performed by applying a low

pulse on the WE or CE input with CE or WE low (respectively) and OE high. The

address is latched on the falling edge of CE or WE, whichever occurs last. The data is

latched by the first rising edge of CE or WE.

PROGRAM:

The device is reprogrammed on a sector basis. If a byte of data within a

sector is to be changed, data for the entire sector must be loaded into the device. The

data in any byte that is not loaded during the programming of its sector will be indetermi-

nate. Once the bytes of a sector are loaded into the device, they are simultaneously

programmed during the internal programming period. After the first data byte has been

loaded into the device, successive bytes are entered in the same manner. Each new

byte to be programmed must have its high to low transition on WE (or CE) within 150

of the low to high transition of WE (or CE) of the preceding byte. If a high to low transi-

tion is not detected within 150

s of the last low to high transition, the load period will

end and the internal programming period will start. A7 to A16 specify the sector address.

AT29C010A

0394E–FLASH–11/02

AT29C010A

The sector address must be valid during each high to low transition of WE (or CE). A0 to

A6 specify the byte address within the sector. The bytes may be loaded in any order;

sequential loading is not required. Once a programming operation has been initiated,

and for the duration of t

, a read operation will effectively be a polling operation.

SOFTWARE DATA PROTECTION:

A software controlled data protection feature is

available on the AT29C010A. Once the software protection is enabled a software algo-

rithm must be issued to the device before a program may be performed. The software

protection feature may be enabled or disabled by the user; when shipped from Atmel,

the software data protection feature is disabled. To enable the software data protection,

a series of three program commands to specific addresses with specific data must be

performed. After the software data protection is enabled the same three program com-

mands must begin each program cycle in order for the programs to occur. All software

program commands must obey the sector program timing specifications. Once set, the

software data protection feature remains active unless its disable command is issued.

Power transitions will not reset the software data protection feature, however the soft-

ware feature will guard against inadvertent program cycles during power transitions.

Once set, software data protection will remain active unless the disable command

sequence is issued.

After setting SDP, any attempt to write to the device without the 3-byte command

sequence will start the internal write timers. No data will be written to the device; how-

ever, for the duration of t

, a read operation will effectively be a polling operation.

After the software data protection’s 3-byte command code is given, a byte load is per-

formed by applying a low pulse on the WE or CE input with CE or WE low (respectively)

and OE high. The address is latched on the falling edge of CE or WE, whichever occurs

last. The data is latched by the first rising edge of CE or WE. The 128 bytes of data must

be loaded into each sector by the same procedure as outlined in the program section

under device operation.

HARDWARE DATA PROTECTION:

Hardware features protect against inadvertent pro-

grams to the AT29C010A in the following ways: (a) V

sense – if V

is below 3.8V

(typical), the program function is inhibited; (b) V

power on delay – once V

has

reached the V

sense level, the device will automatically time out 5 ms (typical) before

programming; (c) Program inhibit – holding any one of OE low, CE high or WE high

inhibits program cycles; and (d) Noise filter—pulses of less than 15 ns (typical) on the

WE or CE inputs will not initiate a program cycle.

PRODUCT IDENTIFICATION:

The product identification mode identifies the device and

manufacturer as Atmel. It may be accessed by hardware or software operation. The

hardware operation mode can be used by an external programmer to identify the correct

programming algorithm for the Atmel product. In addition, users may wish to use the

software product identification mode to identify the part (i.e. using the device code), and

have the system software use the appropriate sector size for program operations. In this

manner, the user can have a common board design for 256K to 4-megabit densities

and, with each density’s sector size in a memory map, have the system software apply

the appropriate sector size.

For details, see Operating Modes (for hardware operation) or Software Product Identifi-

cation. The manufacturer and device code is the same for both modes.

DATA POLLING:

The AT29C010A features DATA polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte loaded will result

in the complement of the loaded data on I/O7. Once the program cycle has been com-

pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may

begin at any time during the program cycle.

0394E–FLASH–11/02

TOGGLE BIT:

In addition to DATA polling the AT29C010A provides another method

for determining the end of a program or erase cycle. During a program or erase opera-

tion, successive attempts to read data from the device will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling

and valid data will be read. Examining the toggle bit may begin at any time during a pro-

gram cycle.

OPTIONAL CHIP ERASE MODE:

The entire device can be erased by using a 6-byte

software code. Please see Software Chip Erase application note for details.

BOOT BLOCK PROGRAMMING LOCKOUT:

The AT29C010A has two designated

memory blocks that have a programming lockout feature. This feature prevents pro-

gramming of data in the designated block once the feature has been enabled. Each of

these blocks consists of 8K bytes; the programming lockout feature can be set indepen-

dently for either block. While the lockout feature does not have to be activated, it can be

activated for either or both blocks.

These two 8K memory sections are referred to as

boot blocks.

Secure code which will

bring up a system can be contained in a boot block. The AT29C010A blocks are located

in the first 8K bytes of memory and the last 8K bytes of memory. The boot block pro-

gramming lockout feature can therefore support systems that boot from the lower

addresses of memory or the higher addresses. Once the programming lockout feature

has been activated, the data in that block can no longer be erased or programmed; data

in other memory locations can still be changed through the regular programming meth-

ods. To activate the lockout feature, a series of seven program commands to specific

addresses with specific data must be performed. Please see Boot Block Lockout Fea-

ture Enable Algorithm.

If the boot block lockout feature has been activated on either block, the chip erase func-

tion will be disabled.

BOOT BLOCK LOCKOUT DETECTION:

A software method is available to determine

whether programming of either boot block section is locked out. See Software Product

Identification Entry and Exit sections. When the device is in the software product identifi-

cation mode, a read from location 00002 will show if programming the lower address

boot block is locked out while reading location 1FFF2 will do so for the upper boot block.

If the data is FE, the corresponding block can be programmed; if the data is FF, the pro-

gram lockout feature has been activated and the corresponding block cannot be pro-

grammed. The software product identification exit mode should be used to return to

standard operation.

Absolute Maximum Ratings*

Temperature Under Bias................................ -55°C to +125°C

Storage Temperature ..................................... -65°C to +150°C

All Input Voltages (including NC Pins)

with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on OE

with Respect to Ground ...................................-0.6V to +13.5V

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

AT29C010A

0394E–FLASH–11/02

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