Features
•
Low-voltage and Standard-voltage Operation
– 1.8 (V
CC
= 1.8V to 3.6V)
Internally Organized 65,536 x 8
Two-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
1 MHz (3.6V), 400 kHz (1.8V) Compatibility
Write Protect Pin for Hardware and Software Data Protection
128-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: 1,000,000 Write Cycles
– Data Retention: 40 Years
•
Lead-free/Halogen-free Devices Available
•
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead LAP and 8-lead SAP Packages
•
Die Sales: Wafer Form, Waffle Pack and Bumped Die
•
•
•
•
•
•
•
•
•
Two-wire Serial
EEPROM
512K (65,536 x 8)
Description
The AT24C512B provides 524,288 bits of serial electrically erasable and programma-
ble read only memory (EEPROM) organized as 65,536 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead Leadless Array
(LAP), and 8-lead SAP packages. In addition, the entire family is available in a 1.8V
(1.8V to 3.6V) version.
AT24C512B
with Three Device
Address Inputs
Preliminary
Table 1.
Pin Configurations
Pin Name
A0–A2
SDA
SCL
WP
NC
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
No Connect
A0
A1
A2
GND
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead Leadless Array
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead SAP
8
7
6
5
1
2
3
4
A0
A1
A2
GND
Bottom View
Bottom View
Rev. 5112A–SEEPR–8/05
1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage ............................................ 4.3V
DC Output Current........................................................ 3.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Figure 1.
Block Diagram
2
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0):
The A2, A1, and A0 pins are device
address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other
AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be
addressed on a single bus system. (Device addressing is discussed in detail under
“Device Addressing,” page 8.) A device is selected when a corresponding hardware and
software match is true. If these pins are left floating, the A2, A1, and A0 pins will be
internally pulled down to GND. However, due to capacitive coupling that may appear
during customer applications, Atmel recommends always connecting the address pins
to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected directly to Vcc, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND. However, due to capacitive coupling that may appear during customer applica-
tions, Atmel recommends always connecting the WP pins to a known state. When using
a pull-up resistor, Atmel recommends using 10kΩ or less.
Memory Organization
AT24C512B, 512K SERIAL EEPROM:
The 512K is internally organized as 512 pages
of 128-bytes each. Random word addressing requires a 16-bit data word address.
3
5112A–SEEPR–8/05
Table 2.
Pin Capacitance
(1)
Applicable over recommended operating range from: T
A
= 25°C, f = 1.0 MHz, V
CC
= +1.8V to +3.6V
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
0
, A
1
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 3.
DC Characteristics
Applicable over recommended operating range from: T
AI
=
−40°C
to +85°C, V
CC
= +1.8V to +3.6V (unless otherwise noted)
Symbol
V
CC1
I
CC1
I
CC2
I
SB1
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Current
Supply Current
Standby Current
(1.8V option)
Input Leakage Current
Output Leakage
Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level
Output Low Level
V
CC
= 3.0V
V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 1.8V
V
CC
= 3.6V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
−0.6
V
CC
x 0.7
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
0.10
0.05
Test Condition
Min
1.8
1.0
2.0
Typ
Max
3.6
2.0
3.0
1.0
3.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.2
µA
µA
V
V
V
V
Units
V
mA
mA
µA
1. V
IL
min and V
IH
max are reference only and are not tested.
4
AT24C512B [Preliminary]
5112A–SEEPR–8/05
AT24C512B [Preliminary]
Table 4.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T
AI
=
−40°C
to +85°C, V
CC
= +1.8V to +3.6V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
0.6
50
5
1.3
0.6
0.05
1.3
0.6
0.6
0
100
0.3
300
0.25
50
5
1,000,000
0.9
Min
Max
400
0.4
0.4
0.05
0.5
0.25
0.25
0
100
0.3
100
0.25
50
5
0.55
Min
2.5-volt
Max
1000
0.4
0.4
0.05
0.5
0.25
0.25
0
100
0.3
100
0.55
Min
3.6-volt
Max
1000
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 kΩ (2.5V, 3.6V), 10 kΩ (1.8V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
50 ns
Input and output timing reference voltages: 0.5 V
CC
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 7).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
5
5112A–SEEPR–8/05
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